SMC128AF NUMONYX [Numonyx B.V], SMC128AF Datasheet - Page 44
SMC128AF
Manufacturer Part Number
SMC128AF
Description
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.SMC128AF.pdf
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CF-ATA registers
8
8.1
8.2
8.2.1
8.2.2
8.2.3
44/82
CF-ATA registers
The following section describes the hardware registers used by the host software to issue
commands to the card. These registers are collectively referred to as the ‘task file’.
Data register (address 1F0h [170h]; offset 0, 8, 9)
The data register is a 16-bit register used to transfer data blocks between the card data
buffer and the host. This register overlaps the error register.
combinations of data register access and explains the overlapped data and error/feature
registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not
defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the
word data register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on
the operations that can be performed.
Table 40.
Error register (address 1F1h [171h]; offset 1, 0Dh read only)
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the status register. The bits are defined in
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
Bit 7 (BBK)
This bit is set when a bad block is detected.
Bit 6 (UNC)
This bit is set when an uncorrectable error is encountered.
Bit 5
This bit is ‘0’.
Error/Feature register
Error/Feature register
Error/Feature register
Word Data register
Even Data register
Odd Data register
Odd Data register
Data register
Data register access
–CE2
0
1
1
0
1
0
0
–CE1
0
0
0
1
0
1
0
A0
X
X
X
X
0
1
1
Table 40
Offset
0, 8, 9
1, Dh
8, 9
0, 8
Dh
9
1
Table
describes the
41. This register
D15 to D0
D15 to D8
D15 to D8
D15 to D8
Data Bus
D7 to D0
D7 to D0
D7 to D0
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