SMC256BFY6 STMICROELECTRONICS [STMicroelectronics], SMC256BFY6 Datasheet - Page 18

• Manufacturer Part Number: SMC256BFY6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical interface
Table 9.
18/91
D15-D00
(PC Card Memory Mode)
D15-D00
(PC Card I/O Mode)
D15-D00
(True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
–INPACK
(PC Card Memory Mode)
–INPACK
(PC Card I/O Mode)
DMARQ
(True IDE Mode)
–IORD
(PC Card Memory Mode)
–IORD
–IORD
(PC Card I/O Mode)
(True IDE Mode)
Signal Name
Signal Description (continued)
Dir.
I/O
O
I
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
23,22,21
1,50
Pin
43
34
Carry the Data, Commands and Status information between
the host and the controller. D00 is the LSB of the Even Byte
of the Word. D08 is the LSB of the Odd Byte of the Word.
Same as PC Card Memory Mode.
All Task File operations occur in Byte mode on D00 to D07
while all data transfers are 16 bit using D00 to D15.
Ground.
Same for all modes.
Same for all modes.
Not used, should not be connected to the host.
The Input Acknowledge is asserted when the Card is
selected and responding to an I/O read cycle at the current
address on the bus. It is used by the host to control the
enable of any input data buffers between the Card and
CPU.
The DMARQ input signal is used to request a DMA data
transfer between the host and the Card. It is asserted to
notify that the Card is ready to transfer data to or from the
host. For Multi-Word DMA transfers, the direction of data
transfer is controlled by -IORD and -IOWR.
DMARQ is used in conjunction with –DMACK to perform
handshaking: the Card waits until –DMACK has been
asserted by the host to de-assert DMARQ, and re-assert it
again if there is still data to be transferred (see
Section
DMARQ is not driven when the Card is not selected.
If the host does not support DMA mode, DMARQ should be
left unconnected.
Not used.
I/O Read strobe generated by the host. It gates I/O data
onto the bus.
Same as PC Card I/O Mode.
10.10).
Description
SMCxxxBF