K4H56038D-TC SAMSUNG [Samsung semiconductor], K4H56038D-TC Datasheet - Page 11

• Manufacturer Part Number: K4H56038D-TC
• Description: 256Mb D-die DDR400 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
2. Timing patterns
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
2. Timing patterns
DDR SDRAM 256Mb D-die (x8, x16)
DDR SDRAM I
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
IDD6
Iout = 0mA
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
Iout = 1mA
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every transfer
*50% of data changing at every transfer
Symbol
IDD4W
IDD2Q
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD7A
IDD0
IDD1
IDD5
Low power
Normal
DD
- CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3)
spec table
105
130
185
220
200
350
1.5
30
25
55
75
4
3
32Mx8
100
130
185
220
200
350
30
25
55
75
1.5
4
3
150
220
250
200
380
110
1.5
75
30
25
55
4
3
16Mx16
105
145
220
250
200
380
1.5
30
25
55
75
4
3
Rev. 1.1 Feb. 2003
DDR SDRAM
(V
DD
=2.7V, T = 10°C)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA Optional
mA
Notes