K4H56038D-TC SAMSUNG [Samsung semiconductor], K4H56038D-TC Datasheet
K4H56038D-TC
Related parts for K4H56038D-TC
K4H56038D-TC Summary of contents
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... DDR SDRAM 256Mb D-die (x8, x16) 256Mb D-die DDR400 SDRAM Specification Revision 1.1 DDR SDRAM Rev. 1.1 Feb. 2003 ...
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... DDR SDRAM 256Mb D-die (x8, x16) 256Mb D-die Revision History Revison 0.0 (June. 2002) 1. First release Revison 0.1 (Aug. 2002) - Changed IDD3P value from 40mA to 55m - Changed IDD3N value from 60mA to 75mA Revision 1.0 (February, 2003) - Modified AC Timing Parameters and Idd value. Revision 1.1 (February, 2003) - Modified tAC value +/-0.7ns => ...
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... DDR SDRAM 256Mb D-die (x8, x16) Key Features • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • ...
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... DDR SDRAM 256Mb D-die (x8, x16) Pin Description DDQ DDQ SSQ SSQ DDQ DDQ SSQ SSQ DDQ DDQ ...
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... DDR SDRAM 256Mb D-die (x8, x16) Package Physical Demension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) 66pin TSOPII / Package dimension DDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0× ...
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... DDR SDRAM 256Mb D-die (x8, x16) / Block Diagram (8Mbx8 4Mbx16 I Banks) Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE 8 /16 CK, CK Data Input Register Serial to parallel 16/ 32 4Mx16/ 2Mx32 4Mx16/ 2Mx32 4Mx16/ 2Mx32 4Mx16/ 2Mx32 Column Decoder Latency & Burst Length ...
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... DDR SDRAM 256Mb D-die (x8, x16) Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(UDM) Input BA0, BA1 Input 12] Input DQ I/O LDQS,(U)DQS I VDDQ Supply VSSQ Supply VDD Supply VSS Supply VREF Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...
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... DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 CKEn CS ...
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... This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV. ...
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... DDR SDRAM 256Mb D-die (x8, x16) DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles high between valid commands. ...
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... Low power 1.5 IDD7A 350 < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle. Iout = 0mA 2. Timing patterns ...
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... DDR SDRAM 256Mb D-die (x8, x16) AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...
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... DDR SDRAM 256Mb D-die (x8, x16) Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...
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... DDR SDRAM 256Mb D-die (x8, x16) AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write to read command delay Clock cycle time ...
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... DQS will be tran sitioning from High logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 7. For command/address input slew rate ≥ 0.5 V/ns 8. For CK & ...
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... DDR SDRAM 256Mb D-die (x8, x16) System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM ...
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... DDR SDRAM 256Mb D-die (x8, x16) System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. Output Figure 2 : Pulldown slew rate test load c ...
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... DDR SDRAM 256Mb D-die (x8, x16) j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions ...