K4S561632C-L1H SAMSUNG [Samsung semiconductor], K4S561632C-L1H Datasheet - Page 3

• Manufacturer Part Number: K4S561632C-L1H
• Description: 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4S561632C
4M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
FUNCTIONAL BLOCK DIAGRAM
clock.
-. Burst length (1, 2, 4, 8 & Full page)
-. CAS latency (2 & 3)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
* Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
GENERAL DESCRIPTION
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
The K4S561632C is 268,435,456 bits synchronous high data rate
K4S561632C-TC/L60
K4S561632C-TC/L7C
K4S561632C-TC/L75
K4S561632C-TC/L1H
K4S561632C-TC/L1L
Latency & Burst Length
Programming Register
WE
Data Input Register
Column Decoder
4M x 16
4M x 16
4M x 16
4M x 16
Part No.
L(U)DQM
LWCBR
166MHz(CL=3)
133MHz(CL=2)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.4 Sept. 2001
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
54pin