IC42S16800D-7TL ISSI [Integrated Silicon Solution, Inc], IC42S16800D-7TL Datasheet
IC42S16800D-7TL
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IC42S16800D-7TL Summary of contents
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... JULY 2008 OVERVIEW ISSI 's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. IS42S81600D IS42S16800D 4M x8x4 Banks 2M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA ...
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... Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed num- ber of locations in a programmed sequence. The registra- tion of an ACTIVE command begins accesses, followed by a READ or WRITE command ...
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IS42S81600D, IS42S16800D PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable CS ...
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IS42S81600D, IS42S16800D PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS ...
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IS42S81600D, IS42S16800D PIN CONFIGURATION 54-ball fBGA for x16 (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch) PACKAGE CODE PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column ...
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... HIGH, disabled. The outputs go to the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device ...
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IS42S81600D, IS42S16800D GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this ...
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IS42S81600D, IS42S16800D COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H ...
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IS42S81600D, IS42S16800D CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down ...
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IS42S81600D, IS42S16800D FUNCTIONAL TRUTH TABLE CS CS RAS RAS CAS CAS RAS RAS CAS RAS CAS CAS Current State Idle ...
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IS42S81600D, IS42S16800D FUNCTIONAL TRUTH TABLE Continued RAS RAS CAS RAS CAS CAS CAS CS CS RAS RAS CAS Current State Read with auto H × × Precharging ...
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IS42S81600D, IS42S16800D FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS CAS CAS CAS CAS CS CS RAS RAS CAS Current State Write Recovering H × × ...
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IS42S81600D, IS42S16800D CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t RC Idle After t RC Illegal Illegal ...
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IS42S81600D, IS42S16800D STATE DIAGRAM Mode Register Set BST Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF SELF exit MRS REF IDLE CKE CKE ACT CKE Row Active CKE BST Read Write Read ...
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IS42S81600D, IS42S16800D ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current ...
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IS42S81600D, IS42S16800D DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter I Operating Current (1) DD1 I Precharge Standby Current DD2P (In Power-Down Mode) I Precharge Standby Current DD2PS (In Power-Down Mode) I Precharge Standby Current (2) DD2N (In Non Power-Down Mode) I ...
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IS42S81600D, IS42S16800D AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 ...
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IS42S81600D, IS42S16800D OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency (CAS Latency = 3) CAS Latency t CAC t Active Command To Read/Write Command Delay Time RCD RAS Latency ( ...
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IS42S81600D, IS42S16800D AC TEST CONDITIONS Input Load t CHI 3.0V 1.4V CLK 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference ...
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... The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. 20 Initialization SDRAMs must be powered up and initialized in a predefined manner. The 128M SDRAM is initialized after the power is applied to V and V (simultaneously) and the clock is stable with DD DDQ DQM High and CKE High. ...
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IS42S81600D, IS42S16800D INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ...
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IS42S81600D, IS42S16800D AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z ...
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IS42S81600D, IS42S16800D SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all ...
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... IS42S16800D REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...
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... IS42S81600D, IS42S16800D BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...
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IS42S81600D, IS42S16800D CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. ...
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... CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possi- bility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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IS42S81600D, IS42S16800D possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be ...
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IS42S81600D, IS42S16800D RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL ...
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IS42S81600D, IS42S16800D CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. ...
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IS42S81600D, IS42S16800D RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL ...
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IS42S81600D, IS42S16800D READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...
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IS42S81600D, IS42S16800D ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ...
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IS42S81600D, IS42S16800D READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN ...
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IS42S81600D, IS42S16800D READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE ...
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IS42S81600D, IS42S16800D READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. ...
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... An example is shown in WRITE to WRITE diagram. Data either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command ...
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IS42S81600D, IS42S16800D WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 07/28/ CLK WRITE NOP NOP BANK, COL n ...
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IS42S81600D, IS42S16800D WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL ...
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IS42S81600D, IS42S16800D WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 07/28/ NOP ...
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IS42S81600D, IS42S16800D WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t ...
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IS42S81600D, IS42S16800D WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t t ...
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IS42S81600D, IS42S16800D ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN m ...
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IS42S81600D, IS42S16800D CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on ...
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IS42S81600D, IS42S16800D CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH (2) A0-A9, A11 COLUMN ...
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IS42S81600D, IS42S16800D PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ...
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IS42S81600D, IS42S16800D POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge ...
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... CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE. READ With Auto Precharge interrupted by a READ ...
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IS42S81600D, IS42S16800D WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to ...
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IS42S81600D, IS42S16800D SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t ...
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IS42S81600D, IS42S16800D READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ...
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IS42S81600D, IS42S16800D SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t ...
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IS42S81600D, IS42S16800D READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ...
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IS42S81600D, IS42S16800D SINGLE WRITE WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW DISABLE AUTO PRECHARGE ...
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IS42S81600D, IS42S16800D SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW DISABLE AUTO ...
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IS42S81600D, IS42S16800D WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11 ROW A10 ROW ...
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IS42S81600D, IS42S16800D WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ...
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IS42S81600D, IS42S16800D ORDERING INFORMATION - V Commercial Range Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S81600D-6T 143 MHz 7 IS42S81600D-7T Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S16800D-6T 166 MHz 6 ...
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... IS42S81600D-7TL Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S16800D-6TL 166 MHz 6 IS42S16800D-6BL 143 MHz 7 IS42S16800D-7TL 143 MHz 7 IC42S16800D-7TL 143 MHz 7 IS42S16800D-7BL 133 MHz 7.5 IS42S16800D-75ETL 133 MHz 7.5 IS42S16800D-75EBL 54-ball BGA, Lead-free ORDERING INFORMATION - V Industrial Range: - Frequency Speed (ns) Order Part No. 143 MHz ...
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PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (54-Ball SEATING PLANE mBGA - 8mm x 13mm MILLIMETERS Sym. Min. Typ. ...
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PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...