K4D26323QG SAMSUNG [Samsung semiconductor], K4D26323QG Datasheet - Page 12

• Manufacturer Part Number: K4D26323QG
• Description: 128Mbit GDDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4D26323QG-GC
Note :
AC OPERATING TEST CONDITIONS
Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.
CAPACITANCE
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Decoupling Capacitance between V
Decoupling Capacitance between V
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input capacitance( CK, CK )
Input capacitance(A
Input capacitance
( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ
Input capacitance(DM0 ~ DM3)
1. V
2. V
All V
All V
DD
SS
and V
and V
DD
SS
pins are connected in chip. All V
pins are connected in chip. All V
IH
SSQ
DDQ
/V
0
Parameter
IL
Parameter
~A
pins are separated each other
Parameter
pins are separated each other.
)
(T
11
A
, BA
= 25°C, f=1MHz)
Output
0
~BA
DD
DDQ
1
)
and V
and V
0
~DQ
SS
SSQ
SSQ
DDQ
31
)
pins are connected in chip.
pins are connected in chip.
(Fig. 1) Output Load Circuit
(T
Z0=50Ω
A
= 0 to 65°C)
- 12 -
Symbol
C
LOAD
C
C
C
C
C
OUT
IN1
IN2
IN3
IN4
V
=30pF
REF
Symbol
C
C
0.50*V
See Fig.1
DC1
DC2
+0.4/V
Value
V
V
1.5
1.0
V
REF
tt
tt
=0.5*V
DDQ
R
REF
T
=50Ω
Min
1.0
1.0
1.0
1.0
1.0
-0.4
DDQ
V
=0.5*V
REF
0.1 + 0.01
0.1 + 0.01
128M GDDR SDRAM
Value
DDQ
Max
5.0
4.0
4.0
6.5
6.5
Rev 1.2(Mar. 2005)
Unit
V/ns
V
V
V
V
V
Unit
uF
uF
Unit
pF
pF
pF
pF
pF
Note
1