AM49DL6408H55FS SPANSION [SPANSION], AM49DL6408H55FS Datasheet
AM49DL6408H55FS
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AM49DL6408H55FS Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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ADVANCE INFORMATION Am49DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply ...
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GENERAL DESCRIPTION Am29DL640H Features The Am29DL640H megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Speed Range Options 2.7–3.3 V Max Access Time (ns) CE#f Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM A21 to A0 A21 to ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & COMMAND CE# REGISTER WP#/ACC DQ15–DQ0 A21–A0 Mux March 12, 2004 ...
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CONNECTION DIAGRAM LB UB A18 A17 G1 ...
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PIN DESCRIPTION A18– Address Inputs (Common) A21–A19 = 3 Address Inputs (Flash Lowest Order Address Pin (PSRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49DL640 AMD DEVICE NUMBER/DESCRIPTION Am49DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit (4 ...
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Table 1. Device Bus Operations—Flash Word Mode; PSRAM Word Mode Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash ± ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins control and selects the device. OE# is the output ...
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the table represents the standby current spec- CC3 ification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses ...
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Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 Bank ...
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Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 Bank ...
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Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank 4 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected ...
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The alternate method intended only for programming equipment requires V on address pin A9 and OE#. ID This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. The ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is ...
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START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 µs protected. Write 60h to any address Remove ...
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Addresses Addresses (Word Mode) (Byte Mode) 10h 20h 11h 22h 12h 24h 13h 26h 14h 28h 15h 2Ah 16h 2Ch 17h 2Eh 18h 30h 19h 32h 1Ah 34h Addresses Addresses (Word Mode) (Byte ...
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Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h 29h 52h 2Ah 54h 2Bh 56h 2Ch 58h 2Dh 5Ah 2Eh 5Ch 2Fh 5Eh 30h 60h 31h 62h 32h 64h 33h 66h 34h ...
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Table 10. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah ...
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FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 11 defines the valid register command sequences. Writing incorrect address and data ...
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Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 11 for program command sequence. Figure 4. Program ...
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data from the non-erasing bank. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation ...
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Table 11. Am29DL640H Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Manufacturer ID Word 4 555 Device ID (Note 9) Word 6 555 SecSi ...
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FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied . . . ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I Reset Leakage Current LR I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) ...
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PSEUDO SRAM DC AND OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Average Operating Current CC1 I s Average Operating Current CC2 V ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address, ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 20. Back-to-back Read/Write Cycle Timings ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of ...
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PSEUDO SRAM AC CHARACTERISTICS Power Up Time When powering up the SRAM, maintain V Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip ...
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PSEUDO SRAM AC CHARACTERISTICS Read Cycle Address CE#1s CE2s OE# Data Out High-Z Notes and t are defined as the time at which the outputs ...
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PSEUDO SRAM AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of ...
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PSEUDO SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled measured from CE1#s going low to the end of write ...
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PSEUDO SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled measured from CE1#s going low to the end of write. ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Chip Program Time Word Mode (Note 3) Notes: 1. Typical program ...
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PHYSICAL DIMENSIONS FLJ073—73-Ball Fine-Pitch Grid Array 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 73X 0. ...
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REVISION SUMMARY Revision A (September 29, 2003) Initial release. Revision A+1 (November 24, 2003) MCP Block Diagram Updated Diagram and reconfigured product selector guide table. CMOS Compatible Changed the V test conditions to ...