M36L0R7060B1ZAQE NUMONYX [Numonyx B.V], M36L0R7060B1ZAQE Datasheet
M36L0R7060B1ZAQE
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M36L0R7060B1ZAQE Summary of contents
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Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package Features ■ Multichip package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multilevel, Burst) Flash memory – 1 die ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36L0R7060T1, M36L0R7060B1 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36L0R7060T1, M36L0R7060B1 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... It must be read in conjunction with the M58LR128HTB and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local Numonyx distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 × ...
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M36L0R7060T1, M36L0R7060B1 Table 1. Signal names Signal name A0-A22 Address inputs DQ0-DQ15 Common Data input/output L Latch Enable input for Flash memory and PSRAM K Burst Clock for Flash memory and PSRAM WAIT Wait Data in Burst Mode for Flash ...
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Description Figure 2. TFBGA connections (top view through package 8/ ...
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... Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. and Table 1: Signal ...
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Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how ...
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M36L0R7060T1, M36L0R7060B1 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When de- asserted (V ), the device is disabled, and goes automatically in low-power Standby mode IH or Deep Power-down mode, ...
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Signal descriptions 2.19 V supply voltage DDQF V provides the power supply for the Flash I/O pins. This allows all outputs to be DDQF powered independently of the Flash core power supplies, V 2.20 V Program supply voltage PPF V ...
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M36L0R7060T1, M36L0R7060B1 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do not ...
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Functional description Table 2. Main operating modes (2)(3) Operation Flash Read Flash Write Flash Address ...
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M36L0R7060T1, M36L0R7060B1 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests ...
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... Figure 5. AC measurement load circuit Table 5. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58LR128HTB and M69KB096AM datasheets for further DC and AC characteristics values and illustrations DDF DDQF DEVICE UNDER TEST 0.1µF 0.1µF C ...
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Package mechanical 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box ...
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M36L0R7060T1, M36L0R7060B1 Table 6. Stacked TFBGA88 8 × × 10 active ball array, 0.8 mm pitch, package mechanical data Symbol Typ 0.850 b 0.350 D 8.000 D1 5.600 ddd E 10.000 E1 7.200 ...
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Part numbering 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multichip package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage ...
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M36L0R7060T1, M36L0R7060B1 8 Revision history Table 8. Document revision history Date 23-May-2006 31-Aug-2006 07-May-2007 13-Nov-2007 Revision 0.1 First release. PSRAM changed to M69KM096AM. Blank and T removed below 0.2 Option in Table 7: Ordering information Document status promoted from Target ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...