M36L0R7050L1 STMICROELECTRONICS [STMicroelectronics], M36L0R7050L1 Datasheet - Page 15

• Manufacturer Part Number: M36L0R7050L1
• Description: 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Table 2.
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = Don’t Care
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet).
5. BCR and RCR only.
6. In the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas
7. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
Operation
in the PSRAM of the M36L0R7060U1 and M36L0R7060L1 both A18 and A19 are used to select the BCR, the RCR or the
DIDR.
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for t
Bus Read
Bus Write
Address Latch V
Output
Disable
Standby
Reset
Word Read
Word Write
Read
Configuration
Register (CR
controlled
method)
Program
Configuration
Register (CR
Controlled)
Output
Disable/No
Operation
Deep Power-
Down
Standby
(7)
(1) (2)
(4)
Operating modes - Standard Asynchronous operation
(5)
V
The Flash memory must
V
V
V
E
X
IH
IL
IL
IL
IL
F
Any Flash memory
mode is allowed.
V
V
V
G
V
X
X
IH
IH
IH
IL
be disabled.
F
W
V
V
V
X
X
X
IH
IH
IL
F
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
F
WAIT
Hi-Z
Hi-Z
(3)
V
V
V
V
V
\_/
L E
X
X
X
IH
IH
IH
IL
IL
V
V
V
IL
IH
IH
P
W
V
V
V
V
V
X
X
IH
IL
IH
IH
IL
P
The PSRAM must be disabled.
V
V
G
V
V
Any PSRAM mode is allowed.
X
X
X
IH
IH
IL
IL
P
UB
V
V
V
X
X
X
X
IL
IL
IL
P
LB
V
V
V
X
X
X
X
IL
IL
IL
P
CR
V
V
V
V
X
X
IH
IL
IL
IL
P
X1(DIDR)
A19 A18
00(RCR)
10(BCR)
(BCR)
V
0 or 00
1 or 10
Address In Valid
Address In Valid
X
X
(RCR)
IL
X
X
X
(6)
Address
Inputs
Other
BCR/
RCR
Data
Functional description
X
X
X
X
ELEH(DP)
Address In/ Data In
Address In/ BCR,
ADQ0-
Address In/ Data
ADQ7
Address In Valid
Address Input
RCR or DIDR
Content Valid
Data Output
Data Input
Out Valid
.
High-Z
High-Z
High-Z
Valid
Hi-Z
Hi-Z
Hi-Z
ADQ15
ADQ8-
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