PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 6

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

3.0 Device Overview
When a legacy ISA bus DMA request is asserted, the
PC87200 will transmit that request to the PC/PCI Primary
Bus Arbiter by encoding it and driving it out the PC87200’s
PCPCIREQ# according to the above; first PCPCIREQ# will
be driven low for one PCICLK period to indicate that the
serial encoded request transfer is starting. Then the
PC87200 will drive each of the next eight bits with the value
of its corresponding DREQ. (NOTE: Channel 4 will always
be driven low.) At the end of the request sequence, the
PC87200 will continue to drive its PCPCIREQ# signal
active, indicating that the request is still being maintained.
In response to the request sequence, the PC/PCI Primary
Bus Arbiter will respond with a PC/PCI DMA encoded grant
transfer when it is granting the PCI bus for a PC/PCI DMA
transfer cycle. The PC/PCI encoded grant transfer will
begin when the PC/PCI Primary Bus Arbiter drives
PCPCIGNT# low for one PCICLK period to indicate the
start of the grant sequence; then the next three
PCPCIGNT# signal PCICLK periods will then contain the
encoded grant value, indicating which legacy ISA DMA
channel is being granted the PC Bus.
After receiving a valid grant from the PC/PCI DMA Arbiter,
the PC87200 will recognize the following I/O accesses as
DMA I/O Reads(Writes) from (to) the granted legacy ISA
DMA channel.
PCI bus address bit 2 (A2) indicates if the cycle is to be a
Terminal Count cycle or not.
For Normal DMA Cycles, PCI bus I/O Reads and Writes
will be translated to legacy ISA DMA Reads and Writes
respectively. For Verify DMA Cycles, only PCI bus I/O
Reads will be translated to legacy ISA DMA Verify cycles.
Normal
Normal TC
Verify
Verify TC
bit 2
DMA Cycle
0
0
0
0
1
1
1
1
Type
bit 1
0
0
1
1
0
0
1
1
0000_0000h
0000_0004h
0000_00C0h
0000_00C4h
I/O Address
bit 0
0
1
0
1
0
1
0
1
DMA
DMA Channel 0 (DACK0#)
DMA Channel 0 (DACK1#)
DMA Channel 0 (DACK2#)
DMA Channel 0 (DACK3#)
RESERVED
DMA Channel 0 (DACK5#)
DMA Channel 0 (DACK6#)
DMA Channel 0 (DACK7#)
(Continued)
TC (A2) PCI Cycle Type
Channel Granted
0
1
0
1
I/O Read/Write
I/O Read/Write
I/O Read
I/O Read.
6
3.5.4 Clock Generation
The PC87200 generates the ISA clock using PCI clock sig-
nal (typically 33 MHz).
A PCICLK divisor (3,4) is programmable through PCI con-
figuration register to generate the ISA clock signal. This
provides support for the generation of ISACLK frequencies
8.33 MHz and 11 MHz off of a 33MHz PCICLK.
Figure 3. shows a block diagram for clock generation within
the PC87200.
PCICLK
Figure 3. PC87200 Clock Generation
PC87200
N
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SYSCLK