CY2304 Cypress Semiconductor Corporation., CY2304 Datasheet
CY2304
Manufacturer Part Number
CY2304
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY2304
Case
SOP8
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Cypress Semiconductor Corporation
Document #: 38-07247 Rev. *C
Features
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
• Zero input-output propagation delay, adjustable by
• Multiple configurations – see “Available Configura-
• Multiple low-skew outputs
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
REF
capacitive load on FBK input
tions” table
— Output-output skew less than 200 ps
— Device-device skew less than 500 ps
Logic Block Diagram
Available Configurations
CY2304-1
CY2304-2
CY2304-2
Device
Bank A or B
FBK from
Bank A
Bank B
PLL
•
Bank A Frequency Bank B Frequency
3901 North First Street
/2
2 × Reference
Reference
Reference
Extra Divider (-2)
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25 A of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the “Available Configurations” table. The CY2304–1
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin.
Reference/2
Reference
Reference
•
CLKA1
CLKB2
CLKA2
CLKB1
FBK
San Jose
3.3V Zero Delay Buffer
•
CLKA1
CLKA2
GND
REF
Pin Configuration
CA 95134
Revised December 7, 2002
1
2
3
4
8-pin SOIC
Top View
•
8
7
6
5
408-943-2600
FBK
V
CLKB1
CLKB2
DD
CY2304