74LV138PW,112 NXP Semiconductors, 74LV138PW,112 Datasheet

IC 3-8 DECODER/DEMUX INV 16TSSOP

74LV138PW,112

Manufacturer Part Number
74LV138PW,112
Description
IC 3-8 DECODER/DEMUX INV 16TSSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Type
Decoder/Demultiplexerr
Datasheet

Specifications of 74LV138PW,112

Circuit
1 x 3:8
Independent Circuits
1
Current - Output High, Low
12mA, 12mA
Voltage Supply Source
Single Supply
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LV138PW
74LV138PW
935174390112
1. General description
2. Features
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 — 15 November 2007
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
amb
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
CC
OH
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
CC
= 3.6 V
amb
= 25 C
CC
Product data sheet
= 3.3 V and

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74LV138PW,112 Summary of contents

Page 1

Rev. 03 — 15 November 2007 1. General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV138N +125 C 74LV138D +125 C 74LV138DB +125 C 74LV138PW +125 C 74LV138BQ +125 C 4. Functional diagram Fig 1. Logic symbol 74LV138_3 Product data sheet Description DIP16 plastic dual in-line package; 16 leads (300 mil) SO16 plastic small outline package ...

Page 3

... NXP Semiconductors Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 138 GND 001aad033 Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 74LV138_3 Product data sheet 3-to-8 line decoder/demultiplexer; inverting 3-to-8 ENABLE DECODER EXITING (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin confi ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND 15, 14, 13, 12, 11, 10 Functional description Table 3. Function table H = HIGH voltage level LOW voltage level don’t care Input Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter P total power dissipation tot DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...

Page 6

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current CC C input capacitance I [1] Typical values are measured at T 74LV138_3 Product data sheet … ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation delay An to Yn; see E3 Yn; see Figure power dissipation capacitance V I [1] All typical values are measured the same as t and PLH PHL [3] Typical values are measured at nominal supply voltage (V ...

Page 8

... NXP Semiconductors 11. Waveforms An, E3 input Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. The inputs An outputs Yn propagation delays Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...

Page 9

... NXP Semiconductors Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load resistance Load capacitance including jig and probe capacitance. L Fig 8. Load circuit for switching times Table 9. Test data Supply voltage Input < 3.6 V 2.7 V 4.5 V ...

Page 10

... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 11. Package outline SOT338-1 (SSOP16) ...

Page 13

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... Document ID Release date 74LV138_3 20071115 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...

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