74AHC157PW,112 NXP Semiconductors, 74AHC157PW,112 Datasheet

IC QUAD 2-INPUT MUX 16TSSOP

74AHC157PW,112

Manufacturer Part Number
74AHC157PW,112
Description
IC QUAD 2-INPUT MUX 16TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCr
Type
Multiplexerr
Datasheet

Specifications of 74AHC157PW,112

Circuit
4 x 2:1
Independent Circuits
1
Current - Output High, Low
8mA, 8mA
Voltage Supply Source
Single Supply
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AHC157PW
74AHC157PW
935263999112
1. General description
2. Features
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with
Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74AHC/AHCT157. The state of the common data select input (S) determines
the particular register from which the data comes. It can also be used as function
generator. The device is useful for implementing highly irregular logic by generating any
four of the 16 different functions of two variables with one variable common. The
74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determine by the logic levels applied to S.
The logic equations are:
The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true)
outputs.
1Y = E
2Y = E
3Y = E
4Y = E
74AHC157; 74AHCT157
Quad 2-input multiplexer
Rev. 02 — 9 November 2007
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
Multiple input enable for easy expansion
Ideal for memory chip select decoding
For 74AHC157 only: operates with CMOS input levels
For 74AHCT157 only: operates with TTL input levels
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
(1I1
(2I1
(3I1
(4I1
S + 1I0
S + 2I0
S + 3I0
S + 4I0
S)
S)
S)
S)
CC
Product data sheet

Related parts for 74AHC157PW,112

74AHC157PW,112 Summary of contents

Page 1

Quad 2-input multiplexer Rev. 02 — 9 November 2007 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. ...

Page 2

... NXP Semiconductors Multiple package options Specified from +85 C and from +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC157D +125 C 74AHCT157D 74AHC157PW +125 C 74AHCT157PW 74AHC157BQ +125 C 74AHCT157BQ 4. Functional diagram S E 1I1 1I0 2I1 2I0 3I1 3I0 ...

Page 3

... NXP Semiconductors 1I0 2 3 1I1 2I0 5 6 2I1 MULTIPLEXER SELECTOR 11 3I0 10 3I1 14 4I0 13 4I1 S 1 Fig 3. Logic symbol 5. Pinning information 5.1 Pinning 74AHC157 74AHCT157 1I0 1I1 2I0 6 2I1 2Y 7 GND 8 Fig 5. Pin configuration SO16, TSSOP16 74AHC_AHCT157_2 Product data sheet 74AHC157; 74AHCT157 ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 to 4I0 2, 5, 11, 14 data inputs from source 0 1I1 to 4I1 3, 6, 10, 13 data inputs from source multiplexer outputs GND 8 ground ( enable input (active LOW supply voltage CC 6 ...

Page 5

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...

Page 6

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions For type 74AHC157 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND ...

Page 7

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 additional per input pin; CC supply current other pins 4 5 input I capacitance C output O capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions C power pF dissipation V = GND capacitance 4 outputs switching via S 1 outputs switching via I For type 74AHCT157 t propagation nI0, nI1 to nY; see pd delay nY; see nY; see ...

Page 9

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Propagation delay input (nI0, nI1 output (nYn) Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...

Page 10

... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch Fig 9. Load circuitry for switching times Table 9. Test data Type Input ...

Page 11

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... Document ID Release date 74AHC_AHCT157_2 20071109 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...

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