L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 7

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
December 2005
FW323 Functional Description
PCI Core
The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow
the FW323 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or
reception, the PCI core arbitrates for the PCI bus and enables the FW323 to become the bus master for reading the
different buffer descriptors and management of the actual data transfers to/from host system memory.
The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support
is a standard power management register interface accessible through the PCI configuration space. Through this
register interface, software is able to transition the FW323 into four distinct power consumption states (D0, D1, D2,
and D3hot). This permits software to selectively increase/decrease the power consumption of the FW323 for
reasons such as periods of system inactivity or power conservation. In addition, the FW323 also includes support
for waking up the system through the generation of a power management event (PME).
The FW323 supports generation of a power management event (PME) while in the D0, D1, D2, D3hot, and D3cold
power states. To facilitate PME generation from the D3cold power state, the FW323 supports the detection of an
auxiliary power supply. If an auxiliary power supply is not present, PME generation from the D3cold power state is
disabled. Refer to the FW322 06/FW323 06 D3cold Application Note for specific implementation details of enabling
and supporting the generation of a PME wakeup event while the FW323 is in the D3cold power state.
The PCI core will support CardBus applications, per the PC Card Standard v8.0, when the CARDBUSN pin is low.
This support includes the CardBus I/O electrical requirements, the CIS (Card Information Structure) pointer,
128 bytes of memory in PCI configuration space for user-defined tuples, an additional Base Address register dedi-
cated to CardBus registers, a serial EEPROM format to load the CIS into PCI configuration space, and the Card-
Bus Function Event registers. The FW323 will also support the CardBus implementation of PCI power
management, including support for the CSTSCHG (CardBus status change) signal. Refer to the Application Note,
Using the FW322 06/FW323 06 in CardBus Applications, for more information.
Agere Systems Inc.
PCI BUS
Figure 2. PCI Core Block Diagram
CONFIGURATION
ADDRESS/DATA
(continued)
MUX
PCI
PCI PHY/Link Open Host Controller Interface
CONTROL
CONTROL
MASTER
SLAVE
PCI SLAVE
PCI MASTER
FW323 06 1394a
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