S3C70F2 Samsung semiconductor, S3C70F2 Datasheet
S3C70F2
Related parts for S3C70F2
S3C70F2 Summary of contents
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... The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of general-purpose applications. ...
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... PRODUCT OVERVIEW FEATURES SUMMARY Memory 512 4-bit data memory (RAM) 2048 8-bit program memory (ROM):S3C70F2 4096 8-bit program memory (ROM):S3C70F4 24 I/O Pins I/O: 18 pins, including 8 high current pins Input only: 6 pins Comparator 4-channel mode: Internal reference (4-bit resolution) 16-step variable reference voltage ...
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... In its standard configuration, the 4096 — 16-byte area for vector addresses — 96-byte instruction reference area — 1920-byte general purpose area (S3C70F2) — 3968-byte general purpose area (S3C70F4) The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used as general-purpose ROM ...
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... WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as general-purpose memory. To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used for the main program and banks 1, 2, and 3 for interrupt service routines. 1-4 S3C70F2/C70F4/P70F4 ...
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... System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware. The system clock can use a crystal, or ceramic oscillation source externally-generated clock signal. To drive S3C70F2/C70F4 using an external clock source, the external clock signal should be input to X inverted signal to X ...
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... CPU operation resumes. I/O PORTS The S3C70F2/C70F4 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FF6H in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions ...
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... L register. BSC data can also be manipulated using direct addressing. COMPARATOR The S3C70F2/C70F4 contains a 4-channel comparator which can be multiplexed to normal input port. — Conversion time: 15.2 µs, 121.6 µs at 4.19 MHz — Two operation modes: ...
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... PRODUCT OVERVIEW BLOCK DIAGRAM 8-Bit Timer/Counter P3.0/TCL0 I/O Port 3 P3.1/TCLO0 P3.2/CLO P4.0 - P4.3 I/O Port 4 I/O Port 5 P5.0 - P5.3 P6.0/KS0 P6.1/KS1 I/O Port 6 P6.2/KS2 P6.3/KS3 Figure 1-1. S3C70F2/C70F4 Simplified Block Diagram 1-8 Basic Timer RESET OUT Interrupt Stack Clock Control Pointer Block Program Internal Counter Interrupts Program Instruction Decoder Status Word ...
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... S3C70F2/C70F4/P70F4 PIN ASSIGNMENTS P1.0/INT0 P1.1/INT1 RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 P1.0/INT0 P1.1/INT1 RESET P0.0/SCK P0.1./SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 Figure 1-2. S3C70F2/C70F4 Pin Assignment Diagram Xout 2 Xin 3 TEST 4 S3C70F2 5 6 S3C70F4 7 (Top View 30-SDIP ...
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... CPU clock output BUZ I/O 2 kHz, 4 kHz, 8 kHz kHz frequency output at 4.19 MHz for buzzer sound NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP. 1-10 Table 1-1. S3C70F2/C70F4 Pin Descriptions Description S3C70F2/C70F4/P70F4 Number Share Pin SCK 8(9) ...
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... — Crystal or ceramic oscillator signal for system clock in out NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP. Table 1-2. Overview of S3C70F2/C70F4 Pin Data SDIP Pin Pin Numbers Names V 1 2,3 Xout, Xin ...
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... IN N Figure 1-3. Pin Circuit Type PULL-UP RESISTOR - P CHANNEL IN SCHMITT TRIGGER Figure 1-4. Pin Circuit Type A-3 1- CHANNEL - CHANNEL RESISTOR ENABLE S3C70F2/C70F4/P70F4 V DD PULL-UP RESISTOR IN SCHMITT TRIGGER Figure 1-5. Pin Circuit Type B DATA OUTPUT DISABLE Figure 1-6. Pin Circuit Type CHANNEL OUT - N CHANNEL ...
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KS57C01502/C01504/P01504 RESISTOR ENABLE DATA CIRCUIT TYPE 4 OUTPUT DISABLE SCHMITT TRIGER Figure 1-7. Pin Circuit Type D-1 PNE V DD DATA - P CHANNEL - OUTPUT N CHANNEL DISABLE Figure 1-8. Pin Circuit Type PULL-UP RESISTOR - ...
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PRODUCT OVERVIEW 1-14 NOTES KS57C01502/C01504/P01504 ...
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... S3C70F2/C70F4/P70F4 14 ELECTRICAL DATA ( Parameter Symbol Supply Voltage Input Voltage Output Voltage Output Current High Output Current Low Operating Temperature Storage Temperature (T = – Parameter Symbol V Input High Ports 4 and 5 IH1 Voltage Ports and RESET ...
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... IN OUT = and X IN OUT = RESET = S3C70F2/C70F4/P70F4 Min Typ Max – – 2 – 2 – – – – – 3 – 20 – – 3 – – – 100 ...
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... S3C70F2/C70F4/P70F4 Table 14-2. D.C. Electrical Characteristics (Concluded – Parameter Symbol I Supply Run mode; V DD1 (1) Crystal oscillator; C1=C2=22pF Current Idle mode; V DD2 Crystal oscillator; C1=C2=22pF Stop mode; V DD3 Stop mode; V NOTES: 1. D.C. electrical values for Supply current (I DD1 to I DD3 ) do not include current drawn through internal pull-up resistor, output port drive currents and comparator ...
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... V Stabilization time DD ( input frequency input high and low – IN level width ( input frequency data are for oscillator characteristics only. S3C70F2/C70F4/P70F4 Min Typ = 2 5.5 V 0.4 – 5.5 V 0.4 – = 3.0 V – – 5.5 V 0.4 – 5.5 V 0.4 – = 3.0 V – – 5.5 V 0.4 – ...
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... S3C70F2/C70F4/P70F4 ( Parameter Symbol C Input IN Capacitance C Output OUT Capacitance C I/O Capacitance IO Table 14-5. Comparator Electrical Characteristics (T = – Parameter Symbol Input Voltage Range Reference Voltage Range Input Voltage Accuracy I Input Leakage Current CIN (T = – ...
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... External SCK source Internal SCK source External SCK source Internal SCK source INT0 INT1, KS0–KS2 Input or 128 / fx as assigned by the IMOD0 register setting. CY S3C70F2/C70F4/P70F4 Min Typ Max 335 – – 50 KCY 1600 / t 2 – 150 KCY 100 – ...
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... S3C70F2/C70F4/P70F4 Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (T = – Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait (1) time NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start- up ...
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... Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request Figure 14-4. A.C. Timing Measurement Points (Except for X Xin 14-8 STOP MODE DATA RETENTION MODE V DDDR 0.8 VDD MEASUREMENT POINTS 0.2 VDD Figure 14-5. Clock Timing Measurement at X S3C70F2/C70F4/P70F4 IDLE MODE NORMAL OPERATING MODE t SREL t WAIT 0.8 VDD 0.2 VDD ) VDD - 0.2 V ...
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... S3C70F2/C70F4/P70F4 TCL RESET INT0, 1 KS0 to KS2 TIL Figure 14-6. TCL Timing t RSL Figure 14-7. Input Timing for RESET t INTL 0.8 VDD 0.2 VDD Figure 14-8. Input Timing for External Interrupts ELECTRICAL DATA t TIH 0.8 VDD 0.2 VDD V 0.2 DD RESET Signal t INTH 14-9 ...
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... ELECTRICAL DATA SCK 14-10 t CKY SIK INPUT DATA KSO OUTPUT DATA Figure 14-9. Serial Data Transfer Timing S3C70F2/C70F4/P70F4 0 0 KSI V 0 0.2 DD ...
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... S3C70F2/C70F4/P70F4 15 MECHANICAL DATA OVERVIEW The S3C70F2/C70F4/P70F4microcontroller is available in a 30-pin SDIP package (Samsung part number 30- SDIP-400) and a 32-SOP package (Samsung part number 30-SOP-450A). #30 #1 (1.30) NOTE: Dimensions are in millimeters. 30-SDIP-400 27.88 MAX 27.48 ± 0.20 0.56 ± 0.10 1.12 ± 0.10 Figure 15-1. 30-SDIP-400 Package Dimensions MECHANICAL DATA #16 #15 1.778 0-15 15-1 ...
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... MECHANICAL DATA #32 #1 (0.43) NOTE: Dimensions are in millimeters. 15-2 32-SOP-450A 20.30 MAX 19.90 0.20 0.40 0.10 Figure 15-2. 30-SOP-450A Package Dimensions S3C70F2/C70F4/P70F4 0-8 #17 + 0.10 #16 0.25 - 0.05 0.10 MAX 1.27 ...
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... S3C70F2/C70F4 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P70F4 is fully compatible with the S3C70F2/C70F4, both in function and in pin configuration. Because of its simple programming requirements, the S3P70F4 is ideal for use as an evaluation chip for the S3C70F2/C70F4 ...
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... P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 NOTE: Figure 16-2. S3P70F4 Pin Assignments (32-SOP Package) 16 Xout 2 Xin S3P70F4 (32-SOP The bolds indicate an OTP pin name. S3C70F2/C70F4/P70F4 DD P6.3/BUZ/SCLK 30 P6.2/KS2/SDAT 29 P6.1/KS1 28 P6.0/KS0 27 P5.3 26 P5.2 25 P5.1 24 P5.0 23 P4.3 22 P4.2 21 P4 ...
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... RESET RESET NOTE means the 32-SOP OTP pin number. Table 16-2. Comparison of S3P70F4 and S3C70F2/C70F4 Features Characteristic Program Memory Operating Voltage ( OTP Programming Mode Pin Configuration EPROM Programmability OPERATING MODE CHARACTERISTICS When 12 supplied to the V operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16– ...
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... Ports 4 and 5 All ports, total T – – stg Table 16-5. D.C. Electrical Characteristics = 2 5.5 V) Conditions and X OUT and X OUT = 4 5 – S3C70F2/C70F4/P70F4 Rating – 0 6.5 – 0 0.3 DD – 0 0.3 DD – 5 – 100 – – 150 Min Typ Max ...
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... S3C70F2/C70F4/P70F4 Table 16-5. D.C. Electrical Characteristics (Continued – Parameter Symbol V V Output Low OL Voltage I OL Ports All output pins except Ports Input High LIH1 Leakage All input pins except X Current I V LIH2 Input Low ...
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... V 10 10% = 5 3 not include current drawn through internal pull-up registers, DD1 DD3 SUPPLY VOLTAGE (V) Figure 16-3. Standard Operating Voltage Range S3C70F2/C70F4/P70F4 Min Typ 6.0MHz – 3.0 4.19MHz 2.0 6.0MHz 1.3 4.19MHz 1.0 6.0MHz – 0.8 4.19MHz 0.6 6.0MHz 0.6 4.19MHz 0.4 – 0.5 ...
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... S3C70F2/C70F4/P70F4 (T = – 2 5 Oscillator Clock Configuration Ceramic Oscillation frequency Xin Xout Oscillator C1 C2 Stabilization time Crystal Oscillation frequency Xin Xout Oscillator C1 C2 Stabilization time External Xin Xout X Clock X level width (t NOTES: 1. Oscillation frequency and Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated ...
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... External SCK source Internal SCK source External SCK source Internal SCK source S3C70F2/C70F4/P70F4 Min Typ Max – – Min Typ Max 0 – – – ...
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... S3C70F2/C70F4/P70F4 Table 16-9. A.C. Electrical Characteristics ( Concluded – Parameter Symbol SCK High, Low Width t SI Setup Time to SIK SCK High t SI Hold Time to KSI SCK High (1) Output Delay for t KSO SCK Interrupt Input INTH High, Low Width ...
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... Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 16–10 Symbol Conditions V – DDDR 2.0 V DDDR DDDR t – SREL Released by RESET t WAIT Released by interrupt S3C70F2/C70F4/P70F4 Min Typ Max 2.0 – 5.5 – 0 – – 17 – – – ...
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... S3C70F2/C70F4/P70F4 FAIL Verify Byte Device Failed START Address= First Location V =5V, V =12. Program One 1ms Pulse Increment X YES Verify 1 Byte Last Address FAIL Compare All Byte PASS Device Passed Figure 16-4. OTP Programming Algorithm S3P70F4 OTP FAIL ...
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... S3P70F4 OTP 16–12 NOTES S3C70F2/C70F4/P70F4 ...