RT8113 RICHTEK [Richtek Technology Corporation], RT8113 Datasheet - Page 18

• Manufacturer Part Number: RT8113
• Description: Single Phase VR11.1 PWM Controller with 7-bit VID
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT8113
1) Modulator Characteristic
The modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) gate-driving
signal. The PWM wave is smoothed out by the output
filter, L
and fed to the inverting input of the error amplifier.
The modulator transfer function is the small-signal transfer
function of V
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 10.
The DC gain of the modulator is the input voltage (V
divided by the peak-to-peak oscillator voltage V
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
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18
f
ΔV
LC
OSC
=
2 x L
OUT
π
OSC
and C
Comparator
Figure 9. Compensation Circuit
OUT
OUT
COMP
PWM
COMP
1
C1
OUT
-
+
/V
x C
EA
Z
FB
COMP
EA
C2
-
+
. The output voltage (V
OUT
REF
-
+
R2
REF
(output voltage over the error
FB
Z
Driver
Driver
FB
C3
Z
R1
IN
Z
R3
IN
V
IN
V
OUT
C
OUT
L
OUT
ESR
) is sensed
OSC
V
. The
OUT
IN
)
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires the output
capacitor to have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as the following equation :
2) Design the compensator
A well-designed compensator regulates the output voltage
to the reference voltage V
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45°C) and the highest
bandwidth (0dB crossing frequency, f
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of -20dB/dec.
According to Figure 10, the location of poles and zeros
are :
Generally, f
pole of modulation. Usually, place f
f
f =
f
f = 0
f
f
P1
P2
P3
ESR
Z1
Z2
0
LOG
=
=
=
2 x R2 x C1
2 x R1 + R3 x C3
2 x C3 x R3
2 x
=
π
π
π
π
2 x C
π
(
1
C1 x C2 x R2
1
Figure 10. Bode PLot of Loop Gain
Z1
C1 + C2
1
1
and f
OUT
f
1
Z1
)
Z2
f
f
x ESR
Z2
LC
are designed to cancel the double
REF
f
f
P2
ESR
with fast transient response
f
C
f
P3
DS8113-02 April 2011
Z1
C
Modulator Gain
Compensation Gain
Closed Loop Gain
) possible. It is also
at a fraction of the
Frequency