RT8113 RICHTEK [Richtek Technology Corporation], RT8113 Datasheet - Page 14

• Manufacturer Part Number: RT8113
• Description: Single Phase VR11.1 PWM Controller with 7-bit VID
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT8113
Dynamic VID
The RT8113 can accept VID input changing while the
controller is running. This allows the output voltage (V
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, V
staircase waveform, but in real application, the bandwidth
of the converter is finite while the staircase waveform needs
infinite bandwidth to follow. Thus, undesired V
(when V
changes down) is often observed in these type of designs.
However, for the RT8113, as mentioned before in the
Soft-Start section, V
when PGOOD = high. This slew rate limiter works as a
low-pass filter of V
waveform finite. By smoothening V
V
hand, C
VID OTF. In most cases, a 1nF to 30nF ceramic capacitor
will be suitable for C
www.richtek.com
14
t
t
t
t
t
t
t
t
t
t
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
OUT
is the delay time from power on reset state to the beginning of V
= 1600μs +
≅
is the soft-start time from V
=
is the
is the soft-start time from V
is the power good delay time.
≅
≅
will no longer overshoot or undershoot. On the other
1600μs.
V
800μs.
SS
BOOT
V
DAC
DAC
dwelling time for V
16μA
will increase the settling time of V
changes up) or undershoot (when V
x C
- V
16μA
OUT
BOOT
0.7V x C
SS
DAC
SS
16μA
DAC
should follow V
.
and makes the bandwidth of V
x Css
slew rate is limited by I
SS
OUT
OUT
OUT
DAC
= V
staircase waveform,
= 0 to V
= V
BOOT
DAC
BOOT
, which is a
OUT
.
OUT
OUT
overshoot
to V
SS2
= V
during
OUT
/C
OUT
DAC
DAC
BOOT
SS
= V
)
.
DAC
Output Voltage Differential Sensing
The RT8113 uses a high-gain low-offset error amplifier for
differential sensing. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (R
pin with the positive remote sense pin of the CPU (V
while the FBRTN pin connects directly to the negative
remote sense pin of the CPU (V
compares V
the output voltage.
No-Load Offset
In Figure 5, I
offset. Either I
operation. Connect a resistor from OFS pin to GND to
activate I
V
is generated.
Connect a resistor from the OFS pin to VCC5 to activate
I
pin. In this case, a positive no-load offset voltage (V
is generated.
V
V
OFSP
.
CCP
OFSN
OFSP
. In this case, a negative no-load offset voltage (V
. I
OFSP
= I
= I
OUT
OFSN
OFSP
OFSN
flows through R
EAP
OFSN
rising.
. I
OFSN
OFSN
(= V
x R
x R
and I
FB
FB
flows through R
DAC
or I
OFSP
=
=
− V
OFSP
6.4 x R
0.8 x R
are used to generate no-load
R
R
ADJ
FB
OFS
OFS
) with the V
is active during normal
from the V
CCN
FB
FB
DS8113-02 April 2011
). The error amplifier
FB
FB
from the FB pin to
) connects the FB
CCP
FB
to regulate
to the FB
OFSN
OFSP
CCP
),
)
)