M36P0R9070E0ZAC STMICROELECTRONICS [STMicroelectronics], M36P0R9070E0ZAC Datasheet - Page 9

• Manufacturer Part Number: M36P0R9070E0ZAC
• Description: 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M36P0R9070E0
2
2.1
2.2
2.3
2.4
Signal descriptions
See
connected to this device.
Address inputs (A0-A24)
Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.
Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write
operations they control the commands sent to the Command Interface of the internal state
machine. The Flash memory is accessed through the Chip Enable signal (E
Write Enable signal (W
and the Write Enable signal (W
E
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to
or from the upper part of the selected address when Upper Byte Enable (UB
The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the
selected address when Lower Byte Enable (LB
disabled, the Data Inputs/ Outputs are high impedance.
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash
memory.
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory.
F
Low, and E
Table 1., Logic Diagram
P
must not be Low at the same time.
F
), while the PSRAM is accessed through the Chip Enable signal (E
and
P
).
Table 2., Signal
P
) is driven Low. When both UB
Names, for a brief overview of the signals
F
2 Signal descriptions
P
) and through the
) is driven Low.
P
and LB
P
are
P
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)