ZL50115 ZARLINK [Zarlink Semiconductor Inc], ZL50115 Datasheet - Page 58

• Manufacturer Part Number: ZL50115
• Description: 32, 64 and 128 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Using both mechanisms provides a robust method of indicating an LOS condition to the downstream TDM
equipment.
8.5
To power up the ZL5011x the following procedure must be used:
•
•
•
This is illustrated in the diagram shown in Figure 22.
8.6
The JTAG interface is used to access the boundary scan logic for board level production testing.
8.7
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•
•
The Core supply must never exceed the I/O supply by more than 0.5V
Both the Core supply and the I/O supply must be brought up together
The System Reset and, if used, the JTAG Reset must remain low until at least 100 µs after the 100 MHz
system clock has stabilised. Note that if JTAG Reset is not used it must be tied low
Direct connection to PowerQUICC™ II (MPC8260) host processor and associated memory, but can
support other processors with appropriate glue logic
TDM Framers and/or Line Interface Units
Ethernet PHY for each MAC port
Power Up sequence
JTAG Interface and Board Level Test Features.
External Component Requirements
SCLK
V
RST
DD
<0.5 V
DC
Figure 22 - Powering Up the ZL5011x
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
10 ns
58
> 100 µs
DC
Core supply (1.8 V)
I/O supply (3.3 V)
Data Sheet
t
t
t