AM79C930VC/W AMD [Advanced Micro Devices], AM79C930VC/W Datasheet - Page 136
![no-image](/images/no-image-200.jpg)
AM79C930VC/W
Manufacturer Part Number
AM79C930VC/W
Description
PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C930VCW.pdf
(161 pages)
- Current page: 136 of 161
- Download datasheet (678Kb)
ISA ACCESS
Notes:
1. CMD = one of: MEMR , MEMW , IOR or IOW .
2. RCMD = one of: MEMR , or IOR .
3. WCMD = one of: MEMW , or IOW .
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.
136
Value
0
1
2
3
4
5
6
7
Parameter
AMD
Symbol
ti16
ti20
ti21
ti23
ti25
ti26
ti30
ti31
ti32
ti34
ti10
ti11
ti12
ti13
ti14
ti15
ti22
ti1
ti2
ti3
ti4
ti7
ti8
ti9
Worst Case
FLASH and SRAM wait states set at “3.”
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
Parameter Description
LA[23:17] valid setup to BALE
BALE
LA[23:17] valid hold from BALE
LA[23:17] valid setup to CMD
SA[16:0] valid setup to CMD
CMD
SA[16:0] valid setup to BALE
Data valid delay from RCMD
Data valid setup to WCMD
SA[16:0] valid hold from CMD
CMD
Data valid hold from RCMD
Data valid hold from WCMD
Data disabled from RCMD
IOCHRDY
IOCHRDY
pulse width
CMD
BALE
Data valid delay from IOCHRDY
LA[23:17] valid hold from CMD
AEN valid setup to CMD
AEN valid hold from CMD
AEN valid setup to BALE
Data enabled from RCMD
to CMD
to CMD
delay from IOCHRDY
to BALE
delay from CMD
delay from CMD
to IOCHRDY
pulse width
pulse width
pulse width
P R E L I M I N A R Y
Am79C930
Test Conditions
Note 1
Note 1
Note 4
Notes 2, 5, 6
Note 3
Note 1
Note 1
Note 2
Note 3
Note 2, 6
Notes 1, 7
Notes 5, 6, 7
Notes 1, 7
Note 1
Note 7
Note 1
Note 1
Note 1
Notes 2, 4
6*TCLKIN
–TCLKIN
Min
–75
–15
60
25
12
80
25
20
20
55
20
35
20
80
15
60
0
0
0
53 X TCLKIN
53 X TCLKIN
130 +
Max
110
20
60
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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