AM79C03 AMD [Advanced Micro Devices], AM79C03 Datasheet - Page 29

• Manufacturer Part Number: AM79C03
• Description: Dual Subscriber Line Audio Processing Circuit (DSLAC) Devices
• Manufacturer: AMD [Advanced Micro Devices]

11. Write Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
12. Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
13. Write AISN, PCM Delay, and Analog Gains
(44h)
(45h)
(50h)
TCS:
RCS:
XE=0
XE = 1
RSVD:
Note:
RSVD:
PCM Delay:
Transmit Analog Gain:
Receive Analog Loss:
AISN coefficient: A, B, C, D, E
* Power-up default value.
Note:
Command
Input Data
Command
Output Data
Command
Input Data
XE = 1 should not be programmed unless the PCM delay is removed (i.e., PCD = 1).
The XE bit is set for both channels when written to either channel. If XE = 1, the
maximum PCM clock rate becomes 4.096 MHz.
Maximum PCLK frequency with PCM delay inserted (PCD = 0) is: 4.096 MHz.
Receive Clock Slot number 0–7
Transmit Clock Slot number 0–7
Transmit on negative edge of PCLK
Transmit on positive edge of PCLK
Reserved. Always write as 0, but 0 is not guaranteed when read.
Reserved. Always write as 0, but 0 is not guaranteed when read.
PCD = 0*
PCD = 1
AX = 0*
AX = 1
AR = 0*
AR = 1
The Analog Impedance Scaling Network (AISN) gain can be varied from –0.9375
to 0.9375 in multiples of 0.0625. The gain coefficient is decoded using the follow-
ing equation:
where h
= 10000 implements a special digital Loopback mode, and a value of ABCDE = 00000
indicates a gain of 0 (cutoff).
AISN
is the gain of the AISN and A, B, C, D, and E = 0 or 1. A value of ABCDE
SLAC Products
Delay inserted (SLAC device compatible)
Delay removed (high speed)
0 dB gain
6.02 dB gain
0 dB loss
6.02 dB loss
h
AISN
RSVD
RSVD
PCD
D
D
D
0
0
0
7
7
7
=
0.0625 A 2
XE
XE
AX
D
D
D
1
1
1
6
6
6
RCS
RCS
AR
D
D
D
4
0
0
0
5
5
5
+
B 2
RCS
RCS
3
D
D
D
A
0
0
1
+
4
4
4
C 2
2
RCS
RCS
D
D
D
+
B
0
0
0
3
3
3
D 2
1
TCS
TCS
+
D
D
D
C
1
1
0
E 2
2
2
2
0
TCS
TCS
–
D
D
D
D
0
0
0
16
1
1
1
TCS
TCS
D
D
D
E
0
1
0
0
0
0
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