ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 41

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The device has two sets of limits the Stratum 4E default limits and the Relaxed Stratum 4E limits (see Table 11 on
page 41). The ST4_LIM bit in Table 27, DPLL Control Register (DPLLCR) Bits is used to select between the two
sets of limits.
17.0
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 24 on page 88, Figure 25 on page 89, Figure 26 on page 90 and Figure 27 on page 91 for the
microprocessor timing.
18.0
The RESET pin is used to reset the ZL50019. When this pin is low, the following functions are performed:
•
•
•
•
•
18.1
The recommended power-up sequence is for the V
power-up of the V
as V
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 31 outputs
drives the STOHZ0 - 15 outputs to high
preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
DD_IO
Power-up Sequence
Microprocessor Port
Device Reset and Initialization
, but should not “lead” the V
Far Upper Limit
Near Upper Limit
Nominal Value
Near Lower Limit
Far Lower Limit
DD_CORE
supply (normally +1.8 V). The V
Table 11 - Multi-Period Hysteresis Limits
Stratum 4E Default Limits
DD_IO
(in 10 ns units)
-82.487 ppm
-64.713 ppm
64.713 ppm
82.487 ppm
supply by more than 0.3 V.
Zarlink Semiconductor Inc.
ZL50019
DD_IO
41
supply (normally +3.3 V) to be established before the
DD_CORE
0 ppm
supply may be powered up at the same time
Relaxed Stratum 4E Limits
(in 10 ns units)
-250 ppm
-240 ppm
240 ppm
250 ppm
Data Sheet