MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 11

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the
output stream channel alignment (i.e., F0i). This feature is useful in compensating for variable path delays caused
by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching
systems.
Each input stream can have its own delay offset value by programming the frame input offset (FOR) registers.
Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming.
Serial Input Frame Alignment Evaluation
The MT90823 provides the frame evaluation (FE) input to determine different data input delays with respect to the
frame pulse F0i.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete
frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high. This signals that a valid
offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before
starting a new measurement cycle.
In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the
ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame
pulse. See Table 10 and Figure 3 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is
connected to VDD).
Memory Block Programming
The MT90823 provides users with the capability of initializing the entire connection memory block in two frames.
Bits 11 to 15 of every connection memory location will be programmed with the pattern stored in bits 5 to 9 of the
IMS register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to
bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to
zero.
Loopback Control
The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped
backed internally to the ST-BUS input for diagnostic purposes.
Serial Interface
Data Rate
2 Mb/s
4 Mb/s
8 Mb/s
Table 1 - Switching Configuration
Zarlink Semiconductor Inc.
Required (MHz)
Master Clock
MT90823
16.384
4.096
8.192
11
Matrix Channel
1,024 x 1,024
2,048 x 2,048
512 x 512
Capacity
Data Sheet