ZL30410QCG1 ZARLINK [Zarlink Semiconductor Inc], ZL30410QCG1 Datasheet
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ZL30410QCG1
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ZL30410QCG1 Summary of contents
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... France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. Multi-service Line Card PLL ZL30410QCC ZL30410QCG1 • Clock generation for ST-BUS and GCI timing Description The ...
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Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Operating Modes and States ...
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Change Summary Changes from March 2006 Issue to November 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 28 Figure 18 Changes from February 2006 Issue to March 2006 Issue. Page, section, figure ...
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Pin Description Pin # Name 1 IC Internal Connection. Leave unconnected. 2 internal bonding Connection. Leave unconnected. 6 GND Ground. Negative power supply internal bonding Connection. Leave unconnected. 9 FCS Filter Characteristic Select (Input). ...
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Pin Description (continued) Pin # Name 21 E3DS3/OC3 E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output (pin 53) to provide ...
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Pin Description (continued) Pin # Name 36 Tclk IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG test logic. If not used, this pin should be pulled up to VDD. 37 Trst IEEE1149.1a Reset Signal (3.3 ...
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Pin Description (continued) Pin # Name 53 C34/C44 Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3 applications) when E3DS3/OC3 is high, or ...
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Functional Description The ZL30410 is designed to provide timing for SDH and SONET equipment conforming to ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates clocks for SDH and PDH equipment operating at DS1, DS2, DS3, E1, and ...
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LOCK HOLDOVER RefAlign MUX Detector Figure 3 - Core PLL Functional Block Diagram 3.2.1 Digitally Controlled Oscillator (DCO) The DCO is an arithmetic unit that continuously generates a stream of numbers that represent the phase-locked clock. These numbers are passed ...
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Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference If the ZL30410 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought into phase alignment with the PLL ...
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C155 : 155.52 MHz clock with nominal 50% duty cycle. The ZL30410 provides the following frame pulses (see Figure 15 "ST-BUS and GCI Output Timing" for details). All frame pulses have the same 125µs period (8kHz frequency): - F0o ...
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MS2,MS1=00 OR RESET=1 MS2,MS1=01 FREE- RESET RUN 10 MS2,MS1=10 forces unconditional return from any state to Free-run Notes: {AUTO} - Automatic internal transition {MANUAL} - User initiated transition --> - External transition Reset State The Reset State must be entered ...
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Holdover State (Holdover Mode) The Holdover State is typically entered for a short duration while synchronization with the network is temporarily disrupted. In Holdover Mode, the ZL30410 generates clocks, which are not locked to an external reference signal but their ...
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JTAG Interface The ZL30410 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990, which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made up of four basic elements, Test Access Port (TAP), ...
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FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the Core PLL. See Table 2 on page 17 for details. FCS 0 Filter corner frequency set to 12 Hz. This selection ...
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C20i Clock Accuracy 0 ppm +4.6 ppm -4.6 ppm -16.6 -13.8 -20 Figure 7 - Primary and Secondary Reference Out of Range Thresholds 5.0 Applications This section provides application examples frequently found in a typical Line Card being part of ...
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MS2,MS1=01 OR MS2,MS1=00 RESET=1 OR MS2,MS1=01 FREE- RESET RUN 10 MS2,MS1=10 forces unconditional return from any state to Free-run Figure 8 - Transition from Free-run to Normal mode 5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL The NORMAL ...
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The Core PLL will automatically return to the Normal state after the reference signal recovers from failure. This transition is shown on the state diagram as a FAIL --> OK change. This change becomes effective when the reference is restored ...
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MHz references. For the 8 kHz input reference, the recovery from Auto Holdover state must transition through the Holdover state to guarantee “hit-less” recovery (for details see section 5.1.3 on page 20). If the reference clock failure persists for ...
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MS2,MS1=00 RESET=1 OR MS2,MS1=01 FREE- RESET RUN 10 MS2,MS1=10 forces unconditional return from any state to Free-run Two types of transitions are possible: • Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock without changing the ...
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GND VDD 6.0 Characteristics 6.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Voltage on any pin 3 Current ...
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Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Operating temperature * Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 Supply current with C20i = 20MHz 2 Supply current with C20i = 0V 3 ...
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ALL SIGNALS t t IF, OF Figure 14 - Timing Parameters Measurement Voltage Levels AC Electrical Characteristics - ST-BUS and GCI Output Timing* Characteristics 1 F16o pulse width low (nom 61 ns) 2 F8o to F16o delay 3 C16o pulse ...
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F16o tc =125µs C16o tc = 61.04 ns F8o tc =125µs C8o tc = 122.07 ns F0o tc =125µs C4o tc = 244.14 ns C2o tc = 488. Electrical Characteristics - DS1 and DS2 Clock Timing* Characteristics 1 ...
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F8o tc =125µs C6o tc = 158.43 ns C1. 647. Electrical Characteristics - C155o and C19o Clock Timing Characteristics 1 C155o pulse width low 2 C155o to C19o rising edge delay 3 C155o to C19o falling ...
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AC Electrical Characteristics - Input to Output Phase Offset (after phase realignment)* Characteristics 1 8 kHz ref pulse width high or low 2 8 kHz ref input to F8o delay 3 1.544 MHz ref: pulse width high or low 4 ...
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AC Electrical Characteristics - Input Control Signals* Characteristics 1 Input controls Setup time 2 Input controls Hold time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8o MS1, MS2 RefSel, FCS, RefAlign E3/DS3 E3DS3/OC3 Figure 19 ...
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Performance Characteristics Performance Characteristics* Characteristics 1 Holdover accuracy (6 Hz filter) 2 Holdover accuracy (12 Hz filter) 3 Holdover stability 4 Capture range 5 Reference Out of Range Threshold Lock Time Filter 7 ...
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Performance Characteristics: Measured Output Jitter - Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Interface Measurement Filter 1 OC-3 65 kHz to 1.3 MHz 155. kHz to1.3 MHz Mbps (Category II) 3 500 Hz to 1.3 MHz ...
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Performance Characteristics: Measured Output Jitter - ITU-T G.747 Jitter Generation Requirements Jitter Interface Measurement Filter 1 DS2 kHz 6312 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics: Measured Output ...
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Performance Characteristics: Measured Output Jitter - ITU-T G.751 Jitter Generation Requirements Jitter Interface Measurement Filter 1 E3 100 Hz to 800 kHz 34368 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30410 G.751 conformance ZL30410 ...
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Performance Characteristics: Measured Output Jitter - ITU-T G.812 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-1 65 kHz to 1.3 MHz optical 2 500 Hz to 1.3 MHz 155.52 Mbps 3 STM-1 65 kHz to 1.3 MHz electrical 155.52 ...
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Performance Characteristics: Measured Output Jitter - ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter Option 1 1 STM-1 65 kHz to 1.3 MHz 155.52 2 500 Hz to 1.3 MHz Mbps 3 STM-1 65 kHz to 1.3 MHz 155.52 ...
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Performance Characteristics: Measured Output Jitter - ETSI EN 300 462-7-1 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-1 65 kHz to 1.3 MHz optical 155.52 2 500 Hz to 1.3 MHz Mbps 3 STM-1 65 kHz to 1.3 MHz ...
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Performance Characteristics - Measured Output Jitter - Unfiltered* Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C4o (4.096 MHz) 4 C6o (6.312 MHz) 5 C8o (8.192 MHz) 6 C8.5o (8.592 MHz) 7 C11o (11.184 MHz) 8 C16o (16.384 ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...