ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 8

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.0
The ZL30108 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame)
signals to SONET/SDH network interface cards. Figure 1 is a functional block diagram which is described in the
following sections.
4.1
The ZL30108 accepts two simultaneous reference input signals and operates on their rising edges. One of two, the
primary reference (REF0) or the secondary reference (REF1) signal is selected as input to the TIE Corrector Circuit
based on the Reference Selection (REF_SEL) input.
4.2
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
REF0 /
REF1
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Reference Select Multiplexer (MUX)
Reference Monitor
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this
information to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the applicable accuracy range defined by the OOR_SEL pin, see Figure 5, Figure 6 and Table 2.
It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
Coarse Frequency Monitor (CFM): This circuit monitors the reference over intervals of approximately
30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Functional Description
Reference Frequency
Precise Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Monitor
Figure 3 - Reference Monitor Circuit
OR
Zarlink Semiconductor Inc.
ZL30108
dis/requalify
timer
8
REF_DIS= reference disrupted (internal signal)
OR
REF_DIS
Mode select
state machine
Data Sheet
REF_FAIL0 /
REF_FAIL1
HOLDOVER