ZL30105_05 ZARLINK [Zarlink Semiconductor Inc], ZL30105_05 Datasheet - Page 30

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ZL30105_05

Manufacturer Part Number
ZL30105_05
Description
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
When the redundant timing card is switched to becoming the active timing card, the system controller should do the
following:
The new active timing card will automatically select a valid input reference REF0 or REF1. If both input references
are available and valid, then REF0 will be chosen over REF1. If the new active timing card should use the same
input reference (REF0 or REF1) as the old active timing card used before it failed, The system controller should do
the following instead:
It is recommended to maintain HMS=1 when switching from redundant to active through the Holdover mode, to
eliminate output phase transients.
When the active timing card is switched to becoming the redundant timing card, the system controller should do the
following:
The ZL30105 allows for the switch from Secondary Master mode to Primary Master mode with no frequency or
phase hits on the output clocks. The switch from Primary Master mode to Secondary Master mode may introduce a
phase transient on the output clocks as the TIE correction circuit is disabled to allow the Secondary master device
to track the active clocks closely.
select Primary Master mode, SEC_MSTR=0
select Automatic mode, MODE_SEL1:0=11
select Holdover (manual) mode, MODE_SEL1:0=01
select Primary Master mode, SEC_MSTR=0
select the required reference (REF0 or REF1) as the input reference
Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL)
select Automatic mode, MODE_SEL1:0=11
select Normal (manual) mode, MODE_SEL1:0=00
select Secondary Master mode, SEC_MSTR=1
select REF2 and REF2_SYNC as the input reference, REF_SEL1=1
Zarlink Semiconductor Inc.
ZL30105
30
Data Sheet

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