ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet - Page 13

• Manufacturer Part Number: ZL30101QDC
• Description: T1/E1 Stratum 3 System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE corrector circuit updating the
delay value thereby forcing the output of the PLL to gradually move back to the original point before it went into
Holdover mode. (see Figure 7). This prevents accumulation of phase in network elements. A logic high (HMS=1)
enables the TIE corrector circuit to update its delay value thereby preventing a large output phase movement after
return to Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output
can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference
switching in the ZL30101 is always hitless unless TIE_CLR is kept low continuously.
REF1
REF1
REF0
Output
Clock
REF0
Output
Clock
TIE_CLR = 0
locked to REF1
locked to REF0
Figure 6 - Timing Diagram of Hitless Reference Switching
Zarlink Semiconductor Inc.
ZL30101
13
REF0
REF1
REF0
REF1
Output
Clock
Output
Clock
TIE_CLR = 1
locked to REF1
locked to REF0
Data Sheet