ZL30100QDC ZARLINK [Zarlink Semiconductor Inc], ZL30100QDC Datasheet - Page 16

• Manufacturer Part Number: ZL30100QDC
• Description: T1/E1 System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30100 entered Holdover mode.
In Freerun mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL is locked and then goes into Holdover mode
(auto or manual), the LOCK pin will initially stay high for 1 s. If at that point the DPLL is still in holdover mode, the
LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full lock-time duration. In
Freerun mode the LOCK pin will go low immediately.
3.5
The output of the DCO is used by the frequency synthesizers to generate the C1.5o, C2o, C4o, C8o, C16o, C32o
and C65o clocks and the F4o, F8o, F16o, F32o and F65o frame pulses which are synchronized to the selected
reference input (REF0 or REF1). The frequency synthesizers use digital techniques to generate output clocks and
advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited
driving capability and should be buffered when driving high capacitance loads.
3.6
As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30100 is based on the inputs MODE_SEL1:0, REF_SEL and HMS.
3.7
The ZL30100 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
4.0
4.1
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 1.
Frequency Synthesizers
State Machine
Master Clock
Out of Range Selection
OOR_SEL
Control and Modes of Operation
0
1
Application
DS1
E1
Table 1 - Out of Range Limits Selection
Telcordia GR-1244-CORE Stratum 4/4E
Zarlink Semiconductor Inc.
ZL30100
Applicable Standard
ETSI ETS 300 011
16
ANSI T1.403
ITU-T G.703
Out Of Range Limits
100 - 130 ppm
64 - 83 ppm
Data Sheet