ISPGDS22 LATTICE [Lattice Semiconductor], ISPGDS22 Datasheet - Page 4

• Manufacturer Part Number: ISPGDS22
• Description: in-system programmable Generic Digital SwitchTM
• Manufacturer: LATTICE [Lattice Semiconductor]

There are three members of the ispGDS family, the ispGDS22,
ispGDS18, and ispGSD14. The numerical portion of the part
name indicates the number of I/O cells available. All of the
devices are available in a DIP package, with the ispGDS22 and
ispGDS14 also available in a PLCC package. Each of the
devices operate identically, with the only difference being the
number of I/O cells available.
The ispGDS devices are all programmed through a four-pin
interface, using TTL level signals. The four dedicated program-
ming pins are named MODE, SDI, SDO, and SCLK. No high-
voltage is needed, as the voltages needed for programming are
generated internally. Programming of the entire device, includ-
ing erasure, can be done in less than one second. During the
programming operation, all I/O pins will be tri-stated. Further
details of the programming process can be found in the In-
System Programming section later in this datasheet.
The I/O cells in each device are divided equally into two banks
(Bank A and Bank B). Each I/O cell can be configured as an
input, an inverting output, a non-inverting output, or set to a fixed
TTL high or low. A switch matrix connects the I/O banks,
allowing an I/O cell in one bank to be connected to any of the I/
O cells in the other bank. A single I/O cell configured as an input
can drive one or more I/O cells in the other bank. The full I/O
macrocell, which is identical for each of the I/O pins, is shown
below. The allowable configurations are shown on the following
page.
The ispGDS family of devices feature In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
when the power is turned off.
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the
programming. The interface signals are Serial Data In (SDI),
Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE)
control.
machine and programming of ispGDS devices please refer to
the ISP Architecture and Programming section in this Data
Book.
ispGDS Family Overview
In-System Programmability
For details on the operation of the internal state
2
CMOS cells will not lose the pattern even
4
The ispGDS family of devices uses a standard JEDEC file, as
used for programmable logic devices, to describe device pro-
gramming information. Popular logic compilers, such as ABEL
and CUPL, can produce the JEDEC files for these devices.
The JEDEC files can be used to program the ispGDS devices in
a number of ways, which are shown in the section titled ISP
Architecture and Programming.
An electronic signature word is provided with every ispGDS
device. It contains 32 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control.
NOTE:
calculations. Changing the electronic signature will alter the
fuse checksum in the JEDEC fusemap.
Device Programming
Electronic Signature
The electronic signature is included in checksum
Specifications ispGDS