CXA3197 Sony Corporation, CXA3197 Datasheet - Page 18

• Manufacturer Part Number: CXA3197
• Description: 10-bit 125MSPS D/A Converter
• Manufacturer: Sony Corporation

When using the multiple CXA3197R in MUX.1A mode, the start timing of the 1/2 frequency-divided clocks
becomes out of phase, producing operation such as that shown in the example below. As a countermeasure,
the MUX.1A mode has a function that matches the start timing of the 1/2 frequency-divided clocks with the
reset signal. When using a PECL level reset signal, input the reset signal to Pins 23 and 24 (RESETP/E,
RESETN/E) and leave Pin 22 (RESET/T) open. When using a TTL level reset signal, input the reset signal to
Pin 22 (RESET/T) and leave Pins 23 and 24 (RESETP/E, RESETN/E) open. The reset polarity can be
switched by the R POLARITY pin (Pin 39). When the R POLARITY pin is High or open, reset is active Low;
when Low, reset is active High. See the timing chart for the detailed timing.
Example when not using the reset signal
Example when using the reset signal
Reset signal
CLK
CLK
CLK DIV2OUT
CLK DIV2OUT
CXA3197R
CXA3197R
CLK DIV2OUT
CLK DIV2OUT
RESET
RESET
CXA3197R
CXA3197R
Reset signal
(when active Low)
DIV2OUT
DIV2OUT
DIV2OUT
DIV2OUT
CLK
CLK
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CXA3197R