CXA3197 Sony Corporation, CXA3197 Datasheet - Page 17

• Manufacturer Part Number: CXA3197
• Description: 10-bit 125MSPS D/A Converter
• Manufacturer: Sony Corporation

Description of Operation
The CXA3197R has four types of operation modes to support various applications. The operation mode is set
by switching the function setting pins (C1, C2 and C3).
Operation Mode Table
The CXA3197R can input data divided into two systems: A (DA0 to DA9) and B (DB0 to DB9), internally
multiplex the data, and output it as an analog signal, making it possible to halve the data rate. This lets the
CXA3197R support the TTL data input level in contrast to the ECL data input level for conventional high-speed
D/A converters. The clock signal and reset signal input levels can be selected from either TTL or PECL
according to the application. (However, setting both signals to either TTL or PECL input level is
recommended.)
1. MUX.1A mode
Set C1, C2 and C3 all Low for this mode.
In MUX.1A mode, the frequency of the clock input from the clock input pin is halved internally, and the 1/2
frequency-divided signal is output at TTL level from the DIV2OUT pin. Data synchronized with the DIV2OUT
signal (the signal output from the DIV2OUT pin) can be obtained by operating the CXA3197R front-end system
with the DIV2OUT signal. The timing at which the data output delay of the CXA3197R front-end system
matches with the hold time during CXA3197R data input can be easily set by inputting this synchronized data
to the data input pins and the DIV2OUT signal to the DIV2IN pin. The data can be divided and input to two
systems: A (DA0 to DA9) and B (DB0 to DB9), internally multiplexed, and extracted as analog output.
MUX.1A
MUX.1B
SELE.A
SELE.B
MUX.2
Mode
Clock input
CXA3197R
C1 C2 C3
front-end
system
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
(MSPS)
10bit
10bit
CLK IN
125
Front-end system data output delay
CXA3197R data input hold time
td – DIV
Data IN
(Mbps)
62.5
125
(DIV2OUT signal)
(Mbps)
AOUT
10bit Data. A
10bit Data. B
125
Outputs CLK/2 at TTL level
High impedance
High impedance
High impedance
High impedance
– 17 –
DIV2OUT pin
Data input pins
Clock input pin
DIV2OUT pin
DIV2IN pin
DA0 to DA9
DB0 to DB9
MUX operation by the internal
CLK/2
MUX operation by the internal
CLK/2
MUX operation by DIV2IN
D/A conversion of side A data
input
D/A conversion of side B data
input
1/2
Description of operation
CXA3197R (MUX.1A mode)
CXA3197R