A1010B ACTEL [Actel Corporation], A1010B Datasheet - Page 9

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A1010B

Manufacturer Part Number
A1010B
Description
ACT 1 Series FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet

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Fu nctional Ti m i ng T est s
AC timing for logic module internal delays is determined
after place and route. The DirectTime Analyzer utility
displays actual timing parameters for circuit delays. ACT 1
devices are AC tested to a “binning” circuit specification.
The circuit consists of one input buffer + n logic modules +
one output buffer (n = 16 for A1010B; n = 28 for A1020B). The
Outpu t Buffer Per for m anc e D e r a t in g (5V)
Note:
Outpu t Buffer Per for m anc e D e r a t in g (3.3V)
Note:
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
12
10
12
10
8
6
4
8
6
4
0.2
0.0
0.3
0.1
V
V
OL
OL
Sink
Sink
0.4
0.2
(Volts)
(Volts)
0.5
0.3
0.6
0.4
Military, worst-case values at 125 C, 4.5 V.
Commercial, worst-case values at 70 C, 4.75 V.
Commercial, worst-case values at 70 C, 4.75 V.
logic modules are distributed along two sides of the device, as
inverting or non-inverting buffers. The modules are
connected through programmed antifuses with typical
capacitive loading.
Propagation delay [t
following AC test specifications.
–10
–12
–10
–12
–4
–6
–8
–4
–6
–8
0
4.0
PD
= (t
3.6
0.5
PLH
V
V
3.2
1.0
A C T
+ t
Source
OH
OH
Source
PHL
(Volts)
(Volts)
)/2] is tested to the
2.8
1.5
1 S eri es FPG As
2.4
2.0
2.0
2.5
1-291

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