A1010B ACTEL [Actel Corporation], A1010B Datasheet - Page 16

• Manufacturer Part Number: A1010B
• Description: ACT 1 Series FPGAs
• Manufacturer: ACTEL [Actel Corporation]

ACT 1 Timing Char act er i st i cs
(Worst-Case Commercial Conditions)
1-298
Input Module Propagation Delays
Parameter Description
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
f
Note:
1.
INYH
INYL
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
P
MAX
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
Pad to Y High
Pad to Y Low
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input Low to High
Input High to Low
Minimum Pulse Width
High
Minimum Pulse Width
Low
Maximum Skew
Minimum Period
Maximum Frequency
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
1
(continued)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
13.2
14.2
‘–3’ Speed
6.5
6.8
6.5
6.8
3.1
3.1
0.9
1.4
2.1
3.1
6.6
4.9
5.6
6.4
7.0
1.2
1.8
75
70
15.4
16.7
‘–2’ Speed
7.5
8.0
7.5
8.0
3.5
3.5
1.1
1.7
2.5
3.6
7.7
5.6
6.4
7.4
8.1
1.3
2.1
65
60
17.6
18.9
‘–1’ Speed ‘Std’ Speed 3.3 V Speed
8.5
9.0
8.5
9.0
4.0
4.0
1.2
1.9
2.8
4.1
8.7
6.4
7.3
8.4
9.2
1.5
2.4
57
53
10.0
10.5
10.0
10.5
20.9
22.3
10.2
10.8
4.7
4.7
1.4
2.2
3.3
4.8
7.5
8.6
9.9
1.8
2.8
48
45
18.2
8.9
9.8
8.9
9.8
20
14.8
10.0
6.8
6.8
2.0
3.2
4.8
7.0
6.7
7.9
8.8
1.5
2.4
55
50
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns