AM29LV642D AMD [Advanced Micro Devices], AM29LV642D Datasheet - Page 29

• Manufacturer Part Number: AM29LV642D
• Manufacturer: AMD [Advanced Micro Devices]

required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts V
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at V
accelerated programming, or device damage may re-
sult.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
May 5, 2006 25022A2
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for operations other than
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Am29LV642D
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S H E E T
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Note: See Table 10 for program command sequence.
Increment Address
Figure 3. Program Operation
Embedded
in progress
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
No
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