CY62177EV30LL-55BAXI Cypress Semiconductor Corporation., CY62177EV30LL-55BAXI Datasheet

CY62177EV30LL-55BAXI

Manufacturer Part Number

CY62177EV30LL-55BAXI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY62177EV30LL-55BAXI.pdf (15 pages)

Specifications of CY62177EV30LL-55BAXI

Pack_quantity

210

Comm_code

85423245

Lead_time

Eccn

3A991B2A

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CY62177EV30LL-55BAXI

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32-Mbit (2 M × 16 / 4 M × 8) Static RAM

Features

■

Cypress Semiconductor Corporation

Document Number: 001-09880 Rev. *I

Logic Block Diagram

Thin small outline package (TSOP) I configurable as 2 M × 16

or as 4 M x 8 static RAM (SRAM)

Very high speed

❐

Wide voltage range

❐

Ultra low standby power

❐

Ultra low active power

❐

Easy memory expansion with CE

Automatic power down when deselected

Complementary Metal Oxide Semiconductor (CMOS) for

optimum speed and power

Available in Pb-free 48-ball TSOP I package

55 ns

2.2 V to 3.7 V

Typical standby current: 3 A

Maximum standby current: 25 A

Typical active current: 4.5 mA at f = 1 MHz

, CE

and OE Features

•

Power- Down

198 Champion Court

Circuit

COLUMN DECODER

DATA IN DRIVERS

32-Mbit (2 M × 16 / 4 M × 8) Static RAM

RAM Array

2M × 16

Functional Description

The CY62177EV30 is a high performance CMOS static RAM

organized as 2 M words by 16 bits and 4 M words by 8 bits. This

device features advanced circuit design to provide ultra low

active current. It is ideal for providing More Battery Life

(MoBL

The device also has an automatic power down feature that

significantly reduces power consumption by 99 percent when

addresses are not toggling. The device can also be put into

standby mode when deselected (CE

BHE and BLE are HIGH). The input and output pins (I/O

I/O

(CE

Byte High Enable and Byte Low Enable are disabled (BHE, BLE

HIGH), or during a write operation (CE

LOW).

To write to the device, take Chip Enables (CE

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O

written into the location specified on the address pins (A

(I/O

address pins (A

Chip Enables (CE

(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte

Low Enable (BLE) is LOW, then data from the memory location

specified by the address pins appear on I/O

Enable (BHE) is LOW, then data from memory appears on I/O

to I/O

description of read and write modes.

Pin #13 of the 48 TSOP I package is an DNU pin that must be

left floating at all times to ensure proper application

). If Byte High Enable (BHE) is LOW, then data from I/O pins

BHE

HIGH or CE

BLE

) are placed in a high impedance state when: deselected

through I/O

•

) in portable applications such as cellular telephones.

. See the

San Jose

through A

LOW), outputs are disabled (OE HIGH), both

) is written to the location specified on the

I/O

Truth Table on page 10

BLE

BYTE

LOW and CE

BHE

CA 95134-1709

–I/O

CY62177EV30 MoBL

). To read from the device, take

Revised December 22, 2011

HIGH) and Output Enable

HIGH or CE

LOW, CE

•

to I/O

through I/O

for a complete

LOW and CE

408-943-2600

HIGH and WE

LOW or both

. If Byte High

through

), is

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