MT48H4M16LFB4-75 IT Micron Semiconductor Products, MT48H4M16LFB4-75 IT Datasheet

MT48H4M16LFB4-75 IT

Manufacturer Part Number

MT48H4M16LFB4-75 IT

Description

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT48H4M16LF.pdf (62 pages)

Current page: 1 of 62
Download datasheet (3Mb)

Mobile SDRAM

MT48H4M16LF – 1 Meg x 16 x 4 banks

Features

• 1.70–1.95V

• Fully synchronous; all signals registered on positive

• Internal pipelined operation; column address can be

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or continuous

• Auto precharge, includes concurrent auto precharge

• Self refresh mode

• 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Partial-array self refresh (PASR) power-saving mode

• On-die temperature-compensated self refresh

• Deep power-down (DPD) mode

• Programmable output drive strength

• Operating temperature ranges

Notes: 1. For continuous page burst, contact factory

Options

• V

• Configurations

• Plastic “green” package

• Timing (cycle time)

• Operating temperature

• Die revision designator

PDF: 09005aef8237ed98/Source: 09005aef8237ed68

64mb_x16_Mobile SDRAM_Y24L_1.fm - Rev. C 10/07 EN

edge of system clock

changed every clock cycle

page

(TCSR)

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

– 1.8V/1.8V

– 4 Meg x 16 (1 Meg x 16 x 4 banks)

– 54-ball VFBGA, 8mm x 8mm

– 7.5ns @ CL = 3 (133 MHz)

– 8ns @ CL = 3 (125 MHz)

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

for availability.

Products and specifications discussed herein are subject to change by Micron without notice.

Marking

4M16

None

-75

-8

Figure 1:

Table 1:

Table 2:

Configuration

Refresh count

Row addressing

Bank addressing

Column addressing

Speed

Grade

-75

-8

Micron Technology, Inc., reserves the right to change products or specifications without notice.

UDQM

DQ14

DQ12

DQ10

DQ8

Clock Rate (MHz)

CL = 2

64Mb: 4 Meg x 16 Mobile SDRAM

104

DQ15

DQ13

DQ11

Address Table

Key Timing Parameters

CL = CAS (READ) latency

DQ9

CLK

A11

54-Ball VFBGA Ball Assignment

(Top View)

CKE

CL = 3

133

125

(Ball down)

Top view

1 Meg x 16 x 4 banks

CL = 2

8ns

4K (A0–A11)

4 (BA0, BA1)

Access Time

CAS#

4 Meg x 16

256 (A0–A7)

BA0

LDQM

RAS#

DQ0

DQ2

DQ4

DQ6

BA1

Features

DQ1

DQ3

DQ5

DQ7

WE#

CL = 3

A10

CS#

6ns

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