MT46H16M16LFBF-6 IT Micron Semiconductor Products, MT46H16M16LFBF-6 IT Datasheet

MT46H16M16LFBF-6 IT

Manufacturer Part Number

MT46H16M16LFBF-6 IT

Description

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT46H16M16LF.pdf (79 pages)

Current page: 1 of 79
Download datasheet (4Mb)

Mobile DDR SDRAM

MT46H16M16LF – 4 Meg x 16 x 4 banks

MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

For the latest data sheet, refer to Micron’s Web site: www.micron.com

Features

• V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

• Four internal banks for concurrent operation

• Data masks (DM) for masking write data—one mask

• Programmable burst lengths: 2, 4, or 8

• Concurrent auto precharge option supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS compatible inputs

• On-chip temperature sensor to control self refresh

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Selectable output drive (DS)

• Clock stop capability

• 64ms refresh period

Table 1:

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__1.fm - Rev. H 3/08 EN

Width

architecture; two data accesses per clock cycle

aligned with data for WRITEs

per byte

rate

Bus

x16

x32

DD/

Number of banks

Bank address balls

Row address balls

Column address balls

Row address balls

Column address balls

Q = 1.70–1.95V

Architecture

Configuration Addressing

Products and specifications discussed herein are subject to change by Micron without notice.

Standard

BA0, BA1

A0–A12

A0–A11

JEDEC-

Option

A0–A8

Page-Size

Reduced

BA0, BA1

Option

A0–A12

A0–A7

–

Table 2:

Notes: 1. Only available for x16 configuration.

Options

• V

• Configuration

• Row size option

• Plastic “green” packages

• Timing – cycle time

• Power

• Operating temperature range

• Design revision

– 1.8V/1.8V

– 16 Meg x 16 (4 Meg x 16 x 4 banks)

– 8 Meg x 32 (2 Meg x 32 x 4 banks)

– JEDEC-standard option

– Reduced page-size option

– 60-ball VFBGA 8mm x 9mm

– 90-ball VFBGA 8mm x 13mm

– 6ns at CL = 3

– 7.5ns at CL = 3

– Standard

– Low I

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

Speed

Grade

-75

-6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mb: x16, x32 Mobile DDR SDRAM

2. Only available for x32 configuration.

2P/I

Key Timing Parameters

CL = 2

Clock Rate (MHz)

83.3

CL = 3

166

133

CL = 2

6.5ns

Access Time

Marking

Features

16M16

8M32

None

CL = 3

-75

5.0ns

6.0ns

-6

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