N74F194D,623 NXP Semiconductors, N74F194D,623 Datasheet - Page 2

• Manufacturer Part Number: N74F194D,623
• Description: IC SHIFT REGISTER 4BIT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74Fr

Specifications of N74F194D,623

• Logic Type: Register, Bidirectional
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Function: Universal
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 933784230623; N74F194D-T; N74F194D-T

Philips Semiconductors
FEATURES
DESCRIPTION
The functional characteristics of the 74F194 4-Bit Bidirectional Shift
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.
The 74F194 design has special logic features which increase the
range of application. The synchronous operation of the device is
determined by two Mode Select inputs, S0 and S1. As shown in the
Mode Select-Function Table, data can be entered and shifted from
left to right (shift right, Q0 Q1, etc.), or right to left (shift left,
Q3 Q2, etc.), or parallel data can be entered, loading all 4 bits of
the register simultaneously. When both S0 and S1 are Low, existing
data is retained in a hold (do nothing) mode. The first and last
stages provide D-type Serial Data inputs (D
multistage shift right or shift left data transfers without interfering
with parallel load operation. Mode Select and data inputs on the
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data
(D
only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when
S0 and S1 are High is transferred to the Q0–Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR) overrides all other
input conditions and forces the Q outputs Low.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20 A in the High state and 0.6mA in the Low state.
April 4, 1989
Shift right and shift left capability
Synchronous parallel and serial data transfer
Easily expanded for both serial and parallel operation
Asynchronous Master Reset
Hold (do nothing) mode
SR
4-bit bidirectional universal shift register
, D
SL
D0–D3
Q0–Q3
S0, S1
PINS
D
D
) can change when the clock is in either state, provided
MR
CP
SR
SL
Parallel data inputs
Serial data input (Shift Right)
Serial data input (Shift Left)
Mode Select inputs
Clock Pulse input (active rising edge)
Asynchronous master Reset input (Active Low)
Data outputs
DESCRIPTION
SR
, D
SL
) to allow
2
PIN CONFIGURATION
ORDERING INFORMATION
16-pin plastic DIP
16-pin plastic SO
DESCRIPTION
74F194
TYPE
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
TYPICAL f
GND
D
D
MR
D0
D1
D2
D3
SR
150MHz
SL
COMMERCIAL RANGE
T
1
2
3
4
5
6
7
8
amb
V
CC
MAX
N74F194N
N74F194D
= 0 C to +70 C
= 5V 10%,
LOAD VALUE HIGH/LOW
SF00167
16
15
14
13
12
10
11
9
SUPPLY CURRENT
1.0mA/20mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
V
Q0
Q1
Q2
Q3
CP
S1
S0
Product specification
CC
TYPICAL
(TOTAL)
853–0354 96224
33mA
74F194
PKG DWG #
SOT109-1
SOT38-4