74LVC595APW,118 NXP Semiconductors, 74LVC595APW,118 Datasheet
74LVC595APW,118
Specifications of 74LVC595APW,118
74LVC595APW-T
935282471118
Related parts for 74LVC595APW,118
74LVC595APW,118 Summary of contents
Page 1
Rev. 01 — 29 May 2007 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register ...
Page 2
... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC595AD +125 C 74LVC595APW +125 C 74LVC595ABQ +125 C 5. Functional diagram Fig 1. Logic symbol 74LVC595A_1 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state Name Description SO16 plastic small outline package; 16 leads; ...
Page 3
... NXP Semiconductors STAGE LATCH Fig 3. Logic diagram Fig 4. Timing diagram 74LVC595A_1 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state STAGES FF0 Rev. 01 — 29 May 2007 74LVC595A STAGE FF7 LATCH CP mna555 Q 7 Z-state Z-state Z-state Z-state mna556 © NXP B.V. 2007. All rights reserved. ...
Page 4
... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC595A GND 8 Fig 5. Pin configuration SO16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin Q[0:7] 15 parallel data output GND 8 Q7S SHCP 11 STCP 74LVC595A_1 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state ...
Page 5
... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input SHCP STCP [ HIGH voltage state LOW voltage state; = LOW-to-HIGH transition don’t care change high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
Page 6
... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
Page 7
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output GND; O current power-off OFF CC leakage current I supply current additional per input pin; CC supply current input 3 capacitance V = GND [1] All typical values are measured at V ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t enable time OE to Qn; see disable time OE to Qn; see dis pulse width SHCP, STCP HIGH or LOW; W see LOW; see set-up time DS to SHCP; see ...
Page 9
... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t hold time DS to SHCP; see recovery time MR to SHCP; see rec maximum SHCP or STCP; see max frequency and output skew time V sk( power dissipation ...
Page 10
... NXP Semiconductors 12. Waveforms SH CP input output Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency ...
Page 11
... NXP Semiconductors SH CP input D S input output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage drops that occur with the output load Fig 9. The data set-up and hold times for the serial data input (DS) ...
Page 12
... NXP Semiconductors SH CP input output Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time ...
Page 13
... NXP Semiconductors Test data is given in Table 9. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 13. Load circuitry for switching times Table 9. Test data ...
Page 14
... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 15
... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 16
... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 17
... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74LVC595A_1 20070529 74LVC595A_1 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register ...
Page 18
... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
Page 19
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Abbreviations ...