74HCT4094D,118 NXP Semiconductors, 74HCT4094D,118 Datasheet
74HCT4094D,118
Manufacturer Part Number
74HCT4094D,118
Description
IC 8STAGE SHIFT/STORE BUS 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet
1.74HCT4094D118.pdf
(23 pages)
Specifications of 74HCT4094D,118
Package / Case
16-SOIC (3.9mm Width)
Logic Type
Shift Register
Output Type
Standard
Function
Serial to Parallel
Number Of Elements
1
Number Of Bits Per Element
8
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counting Sequence
Serial to Serial/Parallel
Number Of Circuits
1
Logic Family
HCT
Propagation Delay Time
43 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74HCT4094D-T
74HCT4094D-T
933715330118
74HCT4094D-T
933715330118
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HCT4094D,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features and benefits
3. Applications
The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin
compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC4094; 74HCT4094 is an 8-stage serial shift register. It has a storage latch
associated with each stage for strobing data from the serial input to parallel buffered
3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common
bus lines. Data is shifted on positive-going clock transitions. The data in each shift register
stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in
the storage register appears at the outputs whenever the output enable (OE) signal is
HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of 74HC4094;
74HCT4094 devices. Serial data is available at QS1 on positive-going clock edges to
allow high-speed operation in cascaded systems with a fast clock rise time. The same
serial data is available at QS2 on the next negative going clock edge. This is used for
cascading 74HC4094; 74HCT4094 devices when the clock has a slow rise time.
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 4 — 19 December 2011
Low-power dissipation
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
Serial-to-parallel data conversion
Remote control holding register
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
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