HEF4014BT,653 NXP Semiconductors, HEF4014BT,653 Datasheet - Page 7

• Manufacturer Part Number: HEF4014BT,653
• Description: IC STATIC SHIFT REG 8BIT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4014BT,653

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Shift Register
• Function: Parallel or Serial to Serial
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 4.5 V ~ 15.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counting Sequence: Serial/Parallel to Parallel
• Number Of Circuits: 1
• Logic Family: HEF4000
• Propagation Delay Time: 40 ns
• Supply Voltage (max): 15.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V, 9 V, 12 V
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933372670653; HEF4014BTD-T; HEF4014BTD-T

NXP Semiconductors
Table 8.
P
12. Waveforms
HEF4014B_6
Product data sheet
Symbol
P
D
Fig 4.
Fig 5.
D
can be calculated from the formulas shown. V
Measurement points are given in
CP to Qn propagation delays and output transition times
The shaded areas indicate where change is permitted for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in
Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP
Dynamic power dissipation P
Parameter
dynamic power
dissipation
CP input
DS input
PE input
D input
V
V
V
V
SS
SS
SS
SS
V
V
V
V
I
I
I
I
V
10 V
15 V
5 V
DD
50 %
50 %
t
t
Qn output
su
su
CP input
Table
Table
50 %
50 %
50 %
Typical formula for P
P
P
P
t
t
D
h
h
D
D
D
V
V
V
9.
9.
= 900
= 4300
= 12000
OH
SS
OL
V
I
Rev. 06 — 2 November 2009
SS
= 0 V; t
50 %
f
i
90 %
f
+ (f
i
f
+ (f
i
V
t
W
+ (f
M
r
= t
o
V
o
f
10 %
o
M
C
t
t
PHL
r
D
t
C
20 ns; T
t
50 %
L
C
)
( W)
L
)
L
)
V
V
DD
V
DD
f
amb
2
DD
clk(max)
2
2
t
f
= 25 C.
50 %
001aaj456
t
PLH
t
t
su
t
50 %
t
Where:
f
f
C
V
su
i
o
(C
DD
= input frequency in MHz;
L
= output frequency in MHz;
= output load capacitance in pF;
L
50 %
= supply voltage in V;
50 %
t
h
f
o
t
) = sum of the outputs.
h
50 %
8-bit static shift register
HEF4014B
001aae559
© NXP B.V. 2009. All rights reserved.
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