HEF4021BT,653 NXP Semiconductors, HEF4021BT,653 Datasheet - Page 6

• Manufacturer Part Number: HEF4021BT,653
• Description: IC STATIC SHIFT REG 8BIT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 4000Br
• Type: Not Requiredr

Specifications of HEF4021BT,653

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Shift Register
• Function: Parallel or Serial to Serial
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counting Sequence: Serial/Parallel to Parallel
• Number Of Circuits: 1
• Logic Family: HEF4000
• Propagation Delay Time: 40 ns
• Supply Voltage (max): 15.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V, 9 V, 12 V
• Supply Voltage (min): 4.5 V
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: SO
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 15V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933372740653; HEF4021BTD-T; HEF4021BTD-T

NXP Semiconductors
Table 7.
V
[1]
HEF4021B_6
Product data sheet
Symbol
t
t
t
t
t
t
f
PLH
t
su
h
W
rec
clk(max)
SS
= 0 V; T
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
Parameter
LOW to HIGH
propagation delay
transition time
set-up time
hold time
pulse width
recovery time
maximum clock
frequency
Dynamic characteristics
amb
= 25 C; for test circuit see
Conditions
CP to Qn
see
PL to Qn
see
Qn; see
DS to CP;
see
Dn to PL;
see
DS to CP;
see
Dn to PL;
see
CP = LOW;
minimum width;
see
PL = HIGH;
minimum width;
see
PL input;
see
CP input;
see
Figure 4
Figure 4
Figure 5
Figure 6
Figure 5
Figure 6
Figure 5
Figure 6
Figure 6
Figure 5
…continued
Figure 4
Figure
Rev. 06 — 27 November 2009
7; unless otherwise specified.
V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
DD
[1]
[1]
Extrapolation formula
88 ns + (0.55 ns/pF)C
39 ns + (0.23 ns/pF)C
32 ns + (0.16 ns/pF)C
78 ns + (0.55 ns/pF)C
39 ns + (0.23 ns/pF)C
32 ns + (0.16 ns/pF)C
10 ns + (1.00 ns/pF)C
9 ns + (0.42 ns/pF)C
6 ns + (0.28 ns/pF)C
L
L
L
L
L
L
L
L
L
8-bit static shift register
Min
-
-
-
-
-
-
-
-
-
+25
+25
+15
+15
50
30
20
40
20
15
15
15
70
30
24
70
30
24
50
40
35
15
20
6
HEF4021B
© NXP B.V. 2009. All rights reserved.
Typ
115
105
50
40
50
40
60
30
20
15
10
25
10
20
10
10
35
15
12
35
15
12
10
13
30
40
5
5
8
0
0
5
5
L
Max
230
100
210
100
120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
80
60
40
in pF).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
6 of 14