74HCT4094N,112 NXP Semiconductors, 74HCT4094N,112 Datasheet

IC 8STAGE SHIFT/STORE BUS 16-DIP

74HCT4094N,112

Manufacturer Part Number
74HCT4094N,112
Description
IC 8STAGE SHIFT/STORE BUS 16-DIP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheets

Specifications of 74HCT4094N,112

Package / Case
16-DIP (0.300", 7.62mm)
Logic Type
Shift Register
Output Type
Standard
Function
Serial to Parallel
Number Of Elements
1
Number Of Bits Per Element
8
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Counting Sequence
Serial to Serial/Parallel
Number Of Circuits
1
Logic Family
HCT
Propagation Delay Time
43 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4484-5
74HCT4094N
74HCT4094N
933670410112
1. General description
2. Features and benefits
3. Applications
The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin
compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC4094; 74HCT4094 is an 8-stage serial shift register. It has a storage latch
associated with each stage for strobing data from the serial input to parallel buffered
3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common
bus lines. Data is shifted on positive-going clock transitions. The data in each shift register
stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in
the storage register appears at the outputs whenever the output enable (OE) signal is
HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of 74HC4094;
74HCT4094 devices. Serial data is available at QS1 on positive-going clock edges to
allow high-speed operation in cascaded systems with a fast clock rise time. The same
serial data is available at QS2 on the next negative going clock edge. This is used for
cascading 74HC4094; 74HCT4094 devices when the clock has a slow rise time.
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 3 — 14 February 2011
Low-power dissipation
ESD protection:
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
Serial-to-parallel data conversion
Remote control holding register
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Product data sheet

Related parts for 74HCT4094N,112

74HCT4094N,112 Summary of contents

Page 1

Rev. 3 — 14 February 2011 1. General description The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the 4094 of the 4000B series specified in compliance with ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74HC4094N 74HCT4094N −40 °C to +125 °C 74HC4094D 74HCT4094D −40 °C to +125 °C 74HC4094DB 74HCT4094DB −40 °C to +125 °C 74HC4094PW 5. Functional diagram 3 CP STR Fig 1. Functional diagram ...

Page 3

... NXP Semiconductors Fig 3. Logic diagram STAGE LATCH 0 STR OE Fig 4. Logic diagram 74HC_HCT4094 Product data sheet D 2 8-STAGE SHIFT CP REGISTER 3 STR 8-BIT STORAGE 1 REGISTER OE 15 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 STAGES QP2 QP4 QP0 QP1 QP3 QP5 All information provided in this document is subject to legal disclaimers. Rev. 3 — ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4094 74HCT4094 STR QP0 QP1 5 QP2 6 7 QP3 GND 8 001aan577 Fig 5. Pin configuration DIP16 and SO16 6.2 Pin description Table 2. Pin description Symbol Pin STR QP0 to QP7 14, 13, 12 QS1, QS2 74HC_HCT4094 Product data sheet 74HC4094; 74HCT4094 ...

Page 5

... NXP Semiconductors 7. Functional description [1] Table 3. Function table Inputs CP OE STR ↑ ↓ ↑ ↑ ↑ ↓ [1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs HIGH voltage level LOW voltage level don’t care; ...

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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...

Page 7

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC4094 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage = −20 μ −20 μ −20 μ −4.0 mA −5.2 mA; V ...

Page 8

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage current OFF-state output current pin; other inputs at V GND supply current 5 ΔI additional supply current other inputs 4 5 per input pin; STR input per input pin ...

Page 9

... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions 74HC4094 t propagation CP to QS1; see pd delay QS2; see QPn; see STR to QPn; see enable time OE to QPn; see ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions t pulse width CP HIGH or LOW; W see Figure STR HIGH; see set-up time D to CP; see STR; see hold time D to CP; see STR ...

Page 11

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions 74HCT4094 t propagation CP to QS1; see pd delay QS2; see QPn; see STR to QPn; see enable time OE to QPn; see 4 disable time OE to QPn; see ...

Page 12

... NXP Semiconductors [ the same as t and t . dis PLZ PHZ [ the same as t and THL TLH [ used to determine the dynamic power dissipation (P PD × V × f × ∑( input frequency in MHz output frequency in MHz output load capacitance in pF supply voltage number of inputs switching; ...

Page 13

... NXP Semiconductors CP input STR input QPn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up and hold times for strobe input ...

Page 14

... NXP Semiconductors OE input LOW-to-OFF OFF-to-LOW HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 11. Enable and disable times Table 8. Measurement points Type 74HC4094 74HCT4094 74HC_HCT4094 Product data sheet GND t PLZ ...

Page 15

... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 12. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC4094 ...

Page 16

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 15. Package outline SOT338-1 (SSOP16) ...

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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product specification All information provided in this document is subject to legal disclaimers. ...

Page 21

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 22

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT4094 Product data sheet 74HC4094 ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline ...

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