74F401PC Fairchild Semiconductor, 74F401PC Datasheet - Page 2

• Manufacturer Part Number: 74F401PC
• Description: IC PARITY GEN/CHKER 16BIT 14DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F401PC

• Logic Type: Parity Generator/Checker
• Number Of Circuits: 16-Bit
• Current - Output High, Low: 1mA, 20mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F401

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Unit Loading/Fan Out
Functional Description
The 74F401 is a 16-bit programmable device which oper-
ates on serial data streams and provides a means of
detecting transmission errors. Cyclic encoding and decod-
ing schemes for error detection are based on polynomial
manipulation in modulo arithmetic. For encoding, the data
stream (message polynomial) is divided by a selected poly-
nomial. This division results in a remainder which is
appended to the message as check bits. For error check-
ing, the bit stream containing both data and check bits is
divided by the same selected polynomial. If there are no
detectable errors, this division results in a zero remainder.
Although it is possible to choose many generating polyno-
mials of a given degree, standards exist that specify a
small number of useful polynomials. The 74F401 imple-
ments the polynomials listed in Table 1 by applying the
appropriate logic levels to the select pins S
The 74F401 consists of a 16-bit register, a Read Only
Memory (ROM) and associated control circuitry as shown
in the block diagram. The polynomial control code pre-
sented at inputs S
selecting the desired polynomial by establishing shift mode
operation on the register with Exclusive OR gates at appro-
priate inputs. To generate the check bits, the data stream is
entered via the Data inputs (D), using the HIGH-to-LOW
Pin Names
S
D
CP
CWE
P
MR
Q
ER
0
–S
2
S
H
H
H
H
L
L
L
L
2
0
, S
Select Code
1
and S
S
H
H
H
H
L
L
L
L
1
Polynomial Select Inputs
Data Input
Clock Input (Operates on HIGH-to-LOW Transition)
Check Word Enable Input
Preset (Active LOW) Input
Master Reset (Active HIGH) Input
Data Output
Error Output
2
is decoded by the ROM,
S
H
H
H
H
L
L
L
L
0
X
X
X
X
X
X
X
X
16
16
16
12
8
8
16
16
0,
X
1
S
X
X
X
X
X
X
7
1
Description
15
14
15
11
12
11
and S
X
5
X
X
X
X
X
X
2
13
3
5
4
2
X
Polynomial
.
1
4
TABLE 1.
1
X
1
1
X
2
7
X
X
2
X
transition of the Clock input (CP). This data is gated with
the most significant output (Q) of the register, and controls
the Exclusive OR gates Figure 1. The Check Word Enable
(CWE) must be held HIGH while the data is being entered.
After the last data bit is entered, the CWE is brought LOW
and the check bits are shifted out of the register and
appended to the data bits using external gating Figure 2.
To check an incoming message for errors, both the data
and check bits are entered through the D input with the
CWE input held HIGH. The 74F401 is not in the data path,
but only monitors the message. The Error Output becomes
valid after the last check bit has been entered into the
74F401 by a HIGH-to-LOW transition of CP. If no detect-
able errors have occurred during the data transmission, the
resultant internal register bits are all LOW and the Error
Output (ER) is LOW. If a detectable error has occurred, ER
is HIGH.
A HIGH on the Master Reset input (MR) asynchronously
clears the register. A LOW on the Preset input (P) asyn-
chronously sets the entire register if the control code inputs
specify a 16-bit polynomial; in the case of 12- or 8-bit check
polynomials only the most significant 12 or 8 register bits
are set and the remaining bits are cleared.
1
4
1
X
2
X
1
1
CRC-16
CRC-16 REVERSE
CRC-12
LRC-8
CRC-CCITT
CRC-CCITT REVERSE
HIGH/LOW
50/33.3
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
U.L.
Remarks
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
Input I
1 mA/20 mA
1 mA/20 mA
IH
OH
/I
/I
IL
OL