HEF4938BT,112 NXP Semiconductors, HEF4938BT,112 Datasheet
![IC DUAL MONO MULTIVIB 16-SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
HEF4938BT,112
Specifications of HEF4938BT,112
HEF4938BT
HEF4938BT
Related parts for HEF4938BT,112
HEF4938BT,112 Summary of contents
Page 1
HEF4938B Dual precision monostable multivibrator Rev. 05 — 6 January 2010 1. General description The HEF4938B is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has an active LOW trigger/retrigger input (nA), an active HIGH trigger/retrigger input (nB), an overriding active ...
Page 2
... NXP Semiconductors 4. Ordering information Table 1. Ordering information − ° All types operate from +85 Type number Package Name Description HEF4938BP DIP16 plastic dual in-line package; 16 leads (300 mil) HEF4938BT SO16 plastic small outline package; 16 leads; body width 3 Functional diagram Fig 1. Functional diagram ...
Page 3
... NXP Semiconductors nREXT/CEXT nCEXT V SS nCD Fig 2. Logic diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration HEF4938B_5 Product data sheet V ref1 enable V ref2 enable HEF4938B 1 16 1CEXT V DD 1REXT/CEXT 2 15 2CEXT 3 14 1CD 2REXT/CEXT 2CD 001aaj604 Rev. 05 — 6 January 2010 HEF4938B ...
Page 4
... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin 1CEXT, 2CEXT 1, 15 1REXT/CEXT, 2REXT/CEXT 2, 14 1CD, 2CD Functional description Table 3. Function table Inputs nA nB ↓ L ↑ HIGH voltage level LOW voltage level don’t care; ↑ = positive-going transition; ↓ = negative-going transition; ...
Page 5
... NXP Semiconductors (1) nB input nA input nCD input nREXT/CEXT input V ref2 V ref1 nQ output T (5) (1) Positive edge triggering. (2) Positive edge re-triggering (pulse lengthening). (3) Negative edge triggering. (4) Reset (pulse shortening). × EXT EXT Fig 5. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V ...
Page 6
... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage ...
Page 7
... NXP Semiconductors Table 6. Static characteristics …continued unless otherwise specified Symbol Parameter I supply current DD C input capacitance I [1] Only one monostable is switching: current present during output pulse (output Q is HIGH). 11. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions Δt pulse width output W variation variation over temperature (T range; see output variation over V voltage range see output variation between same package devices 100 kΩ; EXT = μF C EXT ...
Page 9
... NXP Semiconductors V I nCD input input input output V OL Measurement points are given in Logic levels: V and V are typical output levels that occur with the output load Fig 7. Waveforms showing minimum nA, nB, and nQ pulse widths and recovery and retrigger times HEF4938B_5 Product data sheet ...
Page 10
... NXP Semiconductors 3 Δt W (%) 2 (1) 1 (2) 0 (3) −1 −2 −80 − 100 kΩ 100 nF EXT EXT = 25 ° and T DD amb ( ( ( Fig 8. Typical normalized change in output pulse width as a function of ambient temperature 3 (1) Δt W (%) 2 ( −1 − ° amb DD ( nF. EXT ( 100 nF. ...
Page 11
... NXP Semiconductors Test data is given in Table 9. Definitions for test circuit load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 11. Test circuit Table 9. Test data Supply voltage Input HEF4938B_5 Product data sheet DUT the pulse generator. ...
Page 12
... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
Page 13
... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 14
... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date HEF4938B_5 20100106 Maximum temperature changed to 85 °C throughout. • Modifications: • Section 2 “Features” • Section 9 “Recommended operating conditions” • Section 15 “Legal information” • Abbreviations section removed. HEF4938B_4 20090309 ...
Page 15
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 16
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...