74HC123D,653 NXP Semiconductors, 74HC123D,653 Datasheet

IC MULTIVIBRATR DUAL MONO 16SOIC

74HC123D,653

Manufacturer Part Number
74HC123D,653
Description
IC MULTIVIBRATR DUAL MONO 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC123D,653

Logic Type
Monostable
Package / Case
16-SOIC (3.9mm Width)
Independent Circuits
2
Schmitt Trigger Input
No
Propagation Delay
65ns
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Elements Per Chip
2
Logic Family
HC
Input Bias Current (max)
0.008 mA
Propagation Delay Time
255 ns, 51 ns, 43 ns
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1390-2
74HC123D-T
933713960653
1. General description
2. Features and benefits
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods:
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
1. The basic pulse is programmed by selection of an external resistor (R
2. Once triggered, the basic output pulse width may be extended by retriggering the
3. An internal connection from nRD to the input gates makes it possible to trigger the
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 6 — 14 March 2011
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
ESD protection:
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
capacitor (C
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
circuit by a HIGH-going signal at input nRD as shown in the function table.
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
EXT
).
Product data sheet
EXT
) and

Related parts for 74HC123D,653

74HC123D,653 Summary of contents

Page 1

Dual retriggerable monostable multivibrator with reset Rev. 6 — 14 March 2011 1. General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74HC123N 74HCT123N −40 °C to +125 °C 74HC123D 74HCT123D −40 °C to +125 °C 74HC123DB 74HCT123DB −40 °C to +125 °C 74HC123PW 74HCT123PW −40 °C to +125 °C 74HC123BQ 4 ...

Page 3

... NXP Semiconductors 1RD 11 2RD Fig 2. Logic symbol nRD Fig 4. Logic diagram 74HC_HCT123 Product data sheet Dual retriggerable monostable multivibrator with reset 1CEXT 14 2CEXT 6 1REXT/CEXT 15 2REXT/CEXT mna515 Fig All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 March 2011 74HC123; 74HCT123 ...

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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC123 74HCT123 1RD 2CEXT 6 2REXT/CEXT 7 GND 8 001aaa698 Fig 5. Pin configuration for DIP16, SO16, SSOP16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin 1RD 2CEXT 6 2REXT/CEXT 7 GND 2RD 1CEXT 14 1REXT/CEXT 74HC_HCT123 Product data sheet ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nRD ↓ H ↑ HIGH voltage level LOW voltage level don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; [1] = one HIGH level output pulse; [2] If the monostable was triggered before this condition was established, the pulse will continue as programmed. ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O Δt/ΔV input transition rise and fall rate T ambient temperature amb 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance 74HCT123 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage = −20 μ − LOW-level output voltage = 20 μ 4 input leakage current ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions 74HC123 t propagation nRD, nA nQ; pd delay pF; EXT kΩ; EXT see Figure nRD (reset nQ pF; EXT kΩ; EXT see Figure transition time see Figure pulse width nA LOW; see ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions t retrigger time nA, nB; C rtrig kΩ; V EXT see Figure 10 R external timing see Figure 7 EXT resistor external timing V = 5.0 V; see EXT CC capacitor C power per monostable; PD dissipation V = GND capacitance ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C Symbol Parameter Conditions t pulse width LOW; see nB HIGH; see nRD LOW; see nQ HIGH and nQ LOW 5 see Figure 10 C EXT R EXT C EXT R EXT t retrigger time nA, nB; C rtrig kΩ; V EXT see ...

Page 11

... NXP Semiconductors (ns ° 5 amb ( 100 kΩ EXT ( kΩ EXT ( kΩ EXT ( kΩ EXT Fig 7. Typical output pulse width as a function of the external capacitor value 74HC_HCT123 Product data sheet Dual retriggerable monostable multivibrator with reset 001aaa611 0.8 'K' factor (1) 0.6 (2) (3) 0.4 (4) 0.2 ...

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... NXP Semiconductors 11. Waveforms input M GND input GND V I nRD input GND t PLH output output PHL Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 9. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times ...

Page 13

... NXP Semiconductors nB input nA input nQ output nRD = HIGH Fig 10. Output pulse control using retrigger pulse nB input nRD input nQ output nA = LOW Fig 11. Output pulse control using reset input nRD 74HC_HCT123 Product data sheet Dual retriggerable monostable multivibrator with reset rtrig All information provided in this document is subject to legal disclaimers. ...

Page 14

... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 12. Test circuit for measuring switching times Table 8. Test data Type Input V I 74HC123 ...

Page 15

... NXP Semiconductors 12. Application information 12.1 Timing component connections The basic output pulse width is essentially determined by the values of the external timing components R (1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) Fig 13. Timing component connections 12.2 Power-up considerations When the monostable is powered-up it may produce an output pulse, with a pulse width ...

Page 16

... NXP Semiconductors 12.3 Power-down considerations A large capacitor C the energy stored in this capacitor. When a system containing this device is powered-down or a rapid decrease of V damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode (D diode able to withstand large current surges and connect as shown in Fig 15 ...

Page 17

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 19

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 18. Package outline SOT338-1 (SSOP16) ...

Page 20

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 22

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering Information” and Section 13 “Package outline”, package version ...

Page 23

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 24

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT123 Product data sheet Dual retriggerable monostable multivibrator with reset 16 ...

Page 25

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Application information ...

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