74VHC16373TTR STMicroelectronics, 74VHC16373TTR Datasheet

74VHC16373TTR

Manufacturer Part Number

74VHC16373TTR

Description

IC LATCH 16-BIT D 48-TSSOP

Manufacturer

STMicroelectronics

Series

74VHCr

Datasheet

1.STTH12R06FP.pdf (11 pages)

Specifications of 74VHC16373TTR

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2 V ~ 5.5 V

Independent Circuits

Delay Time - Propagation

5ns

Current - Output High, Low

8mA, 8mA

Operating Temperature

-55°C ~ 125°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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DESCRIPTION

The 74VHC16373 is an advanced high-speed

CMOS 16 BIT D-TYPE LATCH with 3 STATE

OUTPUTS NON INVERTING fabricated with

sub-micron silicon gate and double-layer metal

wiring C

These 16 bit D-TYPE latches are byte controlled

by two latch enable inputs (nLE) and two output

enable inputs(nOE).

While the nLE input is held at a high level, the nQ

outputs will follow the data (D) inputs.

When the nLE is taken LOW, the nQ outputs will

be latched at the logic level of D data inputs.

When the (nOE) input is low, the nQ outputs will

be in a normal logic state (high or low logic level);

when nOE is at high level ,the outputs will be in a

high impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with protec-

tion circuits against static discharge, giving them

2KV ESD immunity and transient excess voltage.

February 2003

HIGH SPEED:

LOW POWER DISSIPATION:

HIGH NOISE IMMUNITY:

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

BALANCED PROPAGATION DELAYS:

OPERATING VOLTAGE RANGE:

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16373

IMPROVED LATCH-UP IMMUNITY

LOW NOISE: V

PLH

NIH

= 5.0 ns (TYP.) at V

= 4 A (MAX.) at T

| = I

(OPR) = 2V to 5.5V

= V

MOS technology.

PHL

NIL

= 8 mA (MIN)

= 28% V

OLP

= 0.9V (MAX.)

=25°C

(MIN.)

WITH 3-STATE OUTPUTS NON INVERTING

= 5V

ORDER CODES

PIN CONNECTION

PACKAGE

TSSOP

16-BIT D-TYPE LATCH

TSSOP

TUBE

74VHC16373

74VHC16373TTR

T & R

1/11

Related parts for 74VHC16373TTR

74VHC16373TTR Summary of contents

Page 1

... All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 WITH 3-STATE OUTPUTS NON INVERTING = 5V ORDER CODES PACKAGE TSSOP PIN CONNECTION 74VHC16373 16-BIT D-TYPE LATCH TSSOP TUBE T & R 74VHC16373TTR 1/11 ...

Page 2

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to ...

Page 3

LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage 3 Low Level Input IL Voltage 3 High Level Output OH Voltage V Low Level Output OL Voltage I High Impedance OZ Output Leakage ...

Page 5

AC ELECTRICAL CHARACTERISTICS (Input t Symbol Parameter V t Propagation Delay 3.3 PLH Time t PHL 3 5.0 5.0 t Propagation Delay 3.3 PLH Time t PHL 3 5.0 5.0 t Output Enable 3.3 ...

Page 6

DYNAMIC SWITCHING CHARACTERISTICS Symbol Parameter V V Dynamic Low OLP Voltage Quiet V OLV Output (note 1, 2) Dynamic High V Voltage Input IHD (note 1, 3) Dynamic Low V Voltage Input ILD (note Worst case ...

Page 7

WAVEFORM PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74VHC16373 7/11 ...

Page 8

WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/11 ...

Page 9

TSSOP48 MECHANICAL DATA DIM. MIN 0. 0.17 c 0.09 D 12.4 E 8.1 BSC E1 6.0 e 0.5 BSC K 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. MIN. 1.2 ...

Page 10

Tape & Reel TSSOP48 MECHANICAL DATA DIM. MIN 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 10/11 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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