CY7C403-25DMB Cypress Semiconductor Corporation., CY7C403-25DMB Datasheet
CY7C403-25DMB
Manufacturer Part Number
CY7C403-25DMB
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C403-25DMB
Date_code
00+
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Features
Functional Description
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
Selection Guide
Logic Block Diagram
Cypress Semiconductor Corporation
Operating Frequency (MHz)
Maximum Operating
Current (mA)
• 64 x 4 (CY7C401 and CY7C403)
• Processed with high-speed CMOS for optimum
• 25-MHz data rates
• 50-ns bubble-through time—25 MHz
• Expandable in word width and/or length
• 5-volt power supply 10% tolerance, both commercial
• Independent asynchronous inputs and outputs
• TTL-compatible interface
• Output enable function available on CY7C403 and
• Capable of withstanding greater than 2001V electro-
• Pin compatible with MMI 67401A/67402A
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first-out memory (FIFO)
speed/power
and military
CY7C404
static discharge
(DI 4 )
DI 0
DI 1
DI 2
DI 3
MR
SI
IR
CONTROL
MASTER
DATAIN
RESET
INPUT
LOGIC
WRITE MULTIPLEXER
READ MULTIPLEXER
WRITE POINTER
READ POINTER
MEMORY
ARRAY
Commercial
Military
•
3901 North First Street
CONTROL
OUTPUT
ENABLE
OUTPUT
DATAIN
LOGIC
C401–1
OE
DO 0
DO 1
DO 2
DO 3
(DO 4 )
SO
OR
7C401/2–5
(CY7C401) NC
(CY7C403) OE
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
The devices accept 4- or 5-bit words at the data input (DI
DI
words stack up at the output (DO
were entered. A read command on the shift out (SO) input
causes the next to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) signal acts
as a flag to indicate when the input is ready to accept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to provide a signal for cascad-
ing.
Parallel expansion for wider words is accomplished by logical-
ly ANDing the IR and OR signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The IR
pin of the receiving device is connected to the SO pin of the
sending device, and the OR pin of the sending device is con-
nected to the SI pin of the receiving device.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
75
5
n
Pin Configurations
) under the control of the shift in (SI) input. The stored
GND
DI
DI
DI
DI
DI
DI
DI
NC
SI
IR
SI
•
0
1
2
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
San Jose
64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
CY7C401
CY7C403
910111213
3 2 1
CY7C401
CY7C403
7C40X–10
DIP
LCC
20
10
75
90
C401–2
16
15
14
13
12
11
10
19
9
C401–3
18
17
16
15
14
V CC
SO
OR
DO
DO
DO
DO
MR
NC
OR
DO
DO
DO
•
0
1
2
3
CY7C401/CY7C403
CY7C402/CY7C404
0
1
2
March 1986 – Revised April 1995
(CY7C402) NC
(CY7C404) OE
CA 95134
7C40X–15
0
DI
DI
DI
DI
15
75
90
GND
DI
DI
DI
SI
– DO
DI
DI
0
1
2
3
IR
SI
0
1
2
3
4
4
5
6
7
8
1
2
3
4
5
6
7
8
9
910111213
3 2 1
CY7C402
CY7C404
n
CY7C402
CY7C404
LCC
) in the order they
•
DIP
20
408-943-2600
19
C401–5
7C40X–25
C401–4
18
17
16
15
14
18
17
16
15
14
13
12
11
10
OR
DO
DO
DO
DO
25
75
90
V CC
SO
OR
DO
DO
DO
DO
DO
MR
0
1
2
3
0
1
2
3
4
0
–
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