X28HC256JI-12 Xicor, X28HC256JI-12 Datasheet

X28HC256JI-12

Manufacturer Part Number

X28HC256JI-12

Description

Manufacturer

Xicor

Datasheet

1.X28HC256JI-12.pdf (24 pages)

Specifications of X28HC256JI-12

Case

PLCC

Date_code

0441+

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Current page: 1 of 24
Download datasheet (111Kb)

V SS

I/O 0

I/O 1

I/O 2

X28HC256

256K

FEATURES

•

PIN CONFIGURATION

A14

A 12

©Xicor, Inc. 1991, 1995 Patents Pending

3859-2.8 8/5/97 T1/C0/D0 EW

A 7

A 6

A 5

A 4

A 3

A 2

A 1

A 0

Access Time: 70ns

Simple Byte and Page Write

—Single 5V Supply

—Self-Timed

Low Power CMOS:

—Active: 60mA

—Standby: 500 A

Software Data Protection

—Protects Data Against System Level

High Speed Page Write Capability

Highly Reliable Direct Write

—Endurance: 100,000 Write Cycles

—Data Retention: 100 Years

Early End of Write Detection

—DATA Polling

—Toggle Bit Polling

— No External High Voltages or V

— No Erase Before Write

— No Complex Programming Algorithms

—No Overerase Problem

Inadvertent Writes

PLASTIC DIP

FLAT PACK

Circuits

X28HC256

CERDIP

SOIC

3859 FHD F02

V CC

A 13

A 8

A 9

A 11

A 10

I/O 7

I/O 6

I/O 5

I/0 4

I/O 3

I/O 0

A 6

A 5

A 4

A 3

A 2

A 1

A 0

™

14 15 16 17 18 19 20

5 Volt, Byte Alterable E

Cell

X28HC256

PLCC

LCC

1 32 31 30

Control

3859 FHD F03

X28HC256

A 8

A 9

A 11

A 10

I/O 7

I/O 6

V SS

DESCRIPTION

The X28HC256 is a second generation high perfor-

mance CMOS 32K x 8 E

Xicor’s proprietary, textured poly floating gate tech-

nology, providing a highly reliable 5 Volt only nonvolatile

memory.

The X28HC256 supports a 128-byte page write opera-

tion, effectively providing a 24 s/byte write cycle and

enabling the entire memory to be typically rewritten in

less than 0.8 seconds. The X28HC256 also features

DATA Polling and Toggle Bit Polling, two methods of

providing early end of write detection. The X28HC256

also supports the JEDEC standard Software Data Pro-

tection feature for protecting against inadvertent writes

during power-up and power-down.

Endurance for the X28HC256 is specified as a minimum

100,000 write cycles per byte and an inherent data

retention of 100 years.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A 10

A 2

A 1

A 0

PROM

X28HC256

TSOP

Characteristics subject to change without notice

PROM. It is fabricated with

32K x 8 Bit

3859 ILL F22

A 3

A 4

A 5

A 6

A 7

A 12

A 14

V CC

A 13

A 8

A 9

A 11

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